AREA		INIT, CODE, READONLY

MODE_USR		EQU	0x10
MODE_FIQ		EQU	0x11
MODE_IRQ		EQU	0x12
MODE_SVC		EQU	0x13
MODE_ABT		EQU	0x17
MODE_UNDEF		EQU	0x1B
MODE_MASK		EQU	0x1F

IRQ_DIS_BIT	EQU	0x80
FIQ_DIS_BIT	EQU	0x40

CPSR_THUMB_ENABLE		EQU		  0x20
CPSR_FIQ_MODE           EQU       MODE_FIQ
CPSR_IRQ_MODE           EQU       MODE_IRQ
CPSR_SUPERVISOR_MODE    EQU       MODE_SVC
CPSR_UNDEF_MODE         EQU       MODE_UNDEF
CPSR_MODE_BITS          EQU       MODE_MASK

RAM_BASE		EQU	0xC0200000		
RAM_LIMIT		EQU	0xC040C000

IRQ_STACK	EQU	RAM_LIMIT
SVC_STACK	EQU	RAM_LIMIT
UNDEF_STACK	EQU SVC_STACK
ABORT_Stack	EQU	UNDEF_STACK

SDRAMBANK0	EQU 0xC0000000
SDRAMA0     EQU	0x80002300
SDRAMV0     EQU 0x00000522
SDRAMA1     EQU 0x80002340
SDRAMV1     EQU 0x00000100

	EXPORT 	__MAIN
__MAIN	
		ENTRY			;Defined to ensure that C runtime system is not linked in.


;ENTRY
	B	Reset
Reset
;Enter IRQ mode and set the IRQ mode stack pionter
	MOV		R0, #MODE_IRQ:OR:IRQ_DIS_BIT:OR:FIQ_DIS_BIT
	MSR		CPSR_c, R0
	LDR		R13, =IRQ_STACK

;Enter SVC mode and set the SVC mode stack pionter
	MOV		R0, #MODE_UNDEF:OR:IRQ_DIS_BIT:OR:FIQ_DIS_BIT
	MSR		CPSR_c, R0
	LDR		R13, =UNDEF_STACK


;Enable Interrupts
	MOV		R0, #MODE_SVC:OR:FIQ_DIS_BIT:OR:IRQ_DIS_BIT
	MSR		CPSR_c, R0
	LDR		R13, =SVC_STACK
	
	
;Enter USR mode
	LDR		R0, =SDRAMA0
	LDR		R1, =SDRAMV0
	STR		R1, [R0]

	LDR		R0, =SDRAMA1
	LDR		R1, =SDRAMV1
	STR		R1, [R0]

	IMPORT	c_entry
	b 	c_entry

	END