//第二章 工程管理與設計輸入 第五節 測試激勵生成器 例
//Verilog 源代碼
//ALU : Arithmetic Logical Unit 算術邏輯運算器

module alu(clk, a, b, opcode, outp_a, outp_s);
input clk;
input [7:0] a, b;		 //input signal
input [2:0] opcode;	 //operation code
output [7:0] outp_s;	 //Synchronous output
output [7:0] outp_a;	 //Asynchronous output

reg [7:0] outp_s;
reg [7:0] outp_a;

always @(posedge clk)
  begin
    case (opcode) /* synthesis full_case */
	  3'h0 : outp_s <= a + b;
	  3'h1 : outp_s <= a - b;
	  3'h2 : outp_s <= a & b;
	  3'h3 : outp_s <= a | b;
	  3'h4 : outp_s <= ~a;
	endcase
end

always @(opcode or a or b)
begin
    case (opcode) 
	  3'h0 : outp_a = a + b;
	  3'h1 : outp_a = a - b;
	  3'h2 : outp_a = a & b;
	  3'h3 : outp_a = a | b;
	  3'h4 : outp_a = ~a;
	endcase
end


endmodule