/*-----------------------------------------------------------------------------
--               Dynamic Shift Register inference using Synplify             --
-------------------------------------------------------------------------------
--
-- GENERAL:
--   Synplify automatically infers Virtex-II Shift-Register cells from 
--     different behavioral descriptions.
--
-- Virtex-II Shift Registers implementations: (See Handbook for more details)
--   - Flip-flops
--   - LUTs 
--      - Any LUT can be configured as a 16-bit shift register. (SRL16)
--      - Shift-in operation is synchronous to a positive clock edge (SRL16)
--          or a negative clock edge (SRL16_1).
--      - Output can be static or dynamically selectable.
--      - A dedicated output allows to cascade any number of 16-bit shift 
--          registers (SRLC16).
--      - Clock enable allows for controlling shift operations. (SRL16E)
--      - To improve shift register's clock to out performance, the last stage
--          can be implemented in register.
--
-- NOTES
--   - Synplify maps to all the above mentionned cells by default as long as:
--       The description represents a set of two or more registers that can be
--       shifted left or right.
--       The contents of only one register can be seen at a time, based on
--       the read address.
--      - Wider shift register descriptions are automatically decomposed into
--          cascaded cells:
--            . SRL16 for static shift register
--            . SRLC16 for dynamic shift register
--
-- ATTRIBUTES:
--   - To prevent automatic inference to shift registers, set the 
--       "syn_srlstyle" attribute to "registers". 
-- Log file message:
--   * Resource Usage Report section (SRL primitives)
--       SRLC16E        16 uses
-------------------------------------------------------------------------------
-- Example: Behavioral description of 2 dimensions dynamic shift register
--          with clock enable
-----------------------------------------------------------------------------*/

module dynamic ( data_in, clk, en, sel, data_out);
  parameter BUS_WIDTH = 8, SRL_DEPTH = 32; // number of clock delays 

  input  [BUS_WIDTH-1 : 0] data_in;
  input                    clk;
  input                    en;
  input  [4 : 0]           sel;
  output [BUS_WIDTH-1 : 0] data_out;

  integer i;
  reg [BUS_WIDTH-1 : 0] lshift_reg [SRL_DEPTH-1 : 0] /* synthesis syn_srlstyle = "select_srl" */;
  // "select_srl"      forces shift register mapping to SRL16 primitives (default)
  // "registers"       forces shift register mapping to registers 
  // "noextractff_srl" forces shift register mapping to SRL16 primitives without the timing optimizing output flip-flops

  always @(posedge clk) begin
    if (en == 1'b1) begin
      for (i=SRL_DEPTH-1; i>0; i=i-1)
        lshift_reg[i] <= lshift_reg[i-1];
      lshift_reg[0] <= data_in;
    end
  end


/*  always @(posedge clk) begin
    if (en == 1'b1) begin
      lshift_reg <= {lshift_reg[SRL_DEPTH-2:0], data_in};
    end
  end
*/
  assign data_out = lshift_reg[sel];

endmodule