/*-----------------------------------------------------------------------------
--           Virtex-II ORCY cell instanciation using Synplify                --
--                         (Sum Of Product)                                  --
-------------------------------------------------------------------------------
--
-- GENERAL:
--   Synplify does not yet support Virtex-II ORCY cells or SOP chain.
--     Instanciation is required.
--
-- Virtex-II ORCY resources: (See Virtex-II Handbook for more details)
--     - ORCY gates are associated with Sum Of Product (SOP) chain and are 
--         designed to implement fast and flexible Sum Of Product functions.
--     - Typical applications are large number of input combinatorial functions
--         that can be decomposed as sum of product.
--
-- NOTES:
--     - Synplify does not yet support Virtex-II ORCY cells or SOP chain,
--         instanciation is required.
-------------------------------------------------------------------------------
-- Example: 64 bits AND function (4 times 16 bits AND gate are ORed together)
--     AND16_ORCY performs a 16 bit AND fonction plus a OR with previous result.
--     SOP is the top module generating the design structure.
-----------------------------------------------------------------------------*/




//----------------------------------------------------------------------------
// Sub-Module : AND_CHAIN
// Description : 16 input AND gate (four times 4 input AND gate + carry chain)
//----------------------------------------------------------------------------
module AND_CHAIN(data_in, carry_in, out_andor_chain);
  input [15:0] data_in;
  input        carry_in;
  output       out_andor_chain;
  wire         VCC = 1'b1;
  wire         out_and_chain;
  wire         dat_out1, data_out2, data_out3;

  AND_LOGIC_OR u4
    ( .sel_data(data_in[15:12]),
      .data_cin(data_out3),
      .carry_in(carry_in),
      .data_out(out_andor_chain) );

  AND_LOGIC u3
    ( .sel_data(data_in[11:8]),
      .data_cin(data_out2),
      .data_out(data_out3) );

  AND_LOGIC u2
    ( .sel_data(data_in[7:4]),
      .data_cin(data_out1),
      .data_out(data_out2) );

  AND_LOGIC u1
    ( .sel_data(data_in[3:0]),
      .data_cin(VCC),
      .data_out(data_out1) );
endmodule


//----------------------------------------------------------------------------
// Sub-Module AND_LOGIC
// Description : 4-input AND gate + carry chain
//----------------------------------------------------------------------------
module AND_LOGIC(sel_data, data_cin, data_out);
  input [3:0] sel_data;
  input       data_cin;
  output      data_out;
  wire        GND = 1'b0;
  wire        VCC = 1'b1;
  wire        and_out;
  
  assign and_out = sel_data[3] & sel_data[2] & sel_data[1] & sel_data[0];
  
  MUXCY muxcy_inst
    ( .DI(GND),
      .CI(data_cin),
      .S(and_out),
      .O(data_out));
endmodule


//----------------------------------------------------------------------------
// Sub-Module AND_LOGIC + ORCY
//----------------------------------------------------------------------------
module AND_LOGIC_OR(sel_data, data_cin, carry_in, data_out);
  input [3:0] sel_data;
  input       data_cin;
  input       carry_in;
  output      data_out;
  wire        data_mux_out;
  wire        GND = 1'b0;
  wire        VCC = 1'b1;
  wire        and_out;
  
  assign and_out = sel_data[3] & sel_data[2] & sel_data[1] & sel_data[0];

  MUXCY muxcy_inst
    ( .DI(GND),
      .CI(data_cin),
      .S(and_out),
      .O(data_mux_out));

  ORCY u5
    ( .I(carry_in),
      .CI(data_mux_out),
      .O(data_out));
endmodule


//----------------------------------------------------------------------------
// Module : SOP_SUBM
// Description : Implementing SOP using MUXCY and ORCY
//----------------------------------------------------------------------------
module SOP_SUBM(and_in, sop_out);
  input  [63:0] and_in;
  output        sop_out;
  wire          out_andor_chain1, out_andor_chain2, out_andor_chain3;
  wire          GND = 1'b0;
  
  AND_CHAIN u4
    ( .data_in(and_in[63:48]),
      .carry_in(out_andor_chain3),
      .out_andor_chain(sop_out) );

  AND_CHAIN u3
    ( .data_in(and_in[47:32]),
      .carry_in(out_andor_chain2),
      .out_andor_chain(out_andor_chain3) );

  AND_CHAIN u2
    ( .data_in(and_in[31:16]),
      .carry_in(out_andor_chain1),
      .out_andor_chain(out_andor_chain2) ); 

  AND_CHAIN u1
    ( .data_in(and_in[15:0]),
      .carry_in(GND),
      .out_andor_chain(out_andor_chain1) );
endmodule