#-- Synplicity, Inc.
#-- Version 7.0.3   
#-- Project file G:\XROADS\INFERENCE_STATUS\SPRO_703\VERILOG\STATE_MACHINE\proj.prj
#-- Written on Thu Feb 14 16:12:38 2002


#add_file options
add_file -verilog "state_machine.v"

#reporting options


#implementation: "synthesis"
impl -add synthesis

#device options
set_option -technology VIRTEX2
set_option -part XC2V40
set_option -package CS144
set_option -speed_grade -5

#compilation/mapping options
set_option -default_enum_encoding default
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1

#map options
set_option -frequency 0.000
set_option -fanout_limit 100
set_option -disable_io_insertion 0
set_option -pipe 0
set_option -modular 0
set_option -retiming 0

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "synthesis/state_machine.edf"
impl -active "synthesis"