module cnt_vlog(CLK,RESET,CE,LOAD,DIR,DIN,COUNT);

    // 4-bit synchronous up-down counter with count enable, // asynchronous reset and synchronous load    input CLK;    input RESET;    input CE, LOAD, DIR;    input [15:0] DIN;    output [15:0] COUNT;    reg [15:0] COUNT; always @(posedge CLK or posedge RESET)begin   if (RESET)      COUNT <= 16'b0;   else begin      if (LOAD)         COUNT <= DIN;      else         if (CE)            if (DIR)               COUNT <= COUNT + 1;            else               COUNT <= COUNT - 1;  endend 

endmodule