?? regcnt.vhd
字號:
library LIB;
use LIB.SYNOPSYS.all;
use LIB.AMD_PACK.all;
entity REGCNT is
port(OPERATION : in REGCNT_OPS;
DATA : in ADDRESS;
CLOCK : in BIT;
OUTPUT : buffer ADDRESS;
ZERO : out BIT);
end REGCNT;
architecture REGCNT_HDL of REGCNT is
begin
process
begin
wait until not CLOCK'stable and CLOCK = '1';
if OPERATION = LOAD then
OUTPUT <= DATA;
elsif OPERATION = DEC then
OUTPUT <= OUTPUT - 1;
end if;
end process;
ZERO <= BIT_OF(OUTPUT = ADDRESS'(others => '0'));
end REGCNT_HDL;
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