library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity prescale_counter is
    Port ( reset   : in  std_logic;
           clk     : in  std_logic;
           counter_out : out std_logic_vector(31 downto 0));
end prescale_counter;

architecture Behavioral of prescale_counter is
  signal counter : std_logic_vector(31 downto 0); 
begin
pre_counter_process:process(clk,reset)
  begin 
    if reset = '0' then
      counter(1 downto 0) <= "00";
    elsif rising_edge(clk) then
      counter(1 downto 0) <= counter(1 downto 0) + '1';
    end if;
  end process;
  
counter_process:process(clk,reset)
  begin
    if reset = '0' then
      counter(31 downto 2) <= (others => '0');
    elsif rising_edge(clk) then
      if (counter(1 downto 0) = "11")then
      counter(31 downto 2) <= counter(31 downto 2) + 1;
      end if;
    end if;
  end process;  

counter_out<=counter;

end Behavioral;