[COREGEN.VHDL Component Instantiation.tenths]type=templatetext000=" "text001=" "text002="-- The following code must appear in the VHDL architecture header:"text003=" "text004="component tenths"text005="    port ("text006="    Q: OUT std_logic_VECTOR(3 downto 0);"text007="    CLK: IN std_logic;"text008="    Q_THRESH0: OUT std_logic;"text009="    CE: IN std_logic;"text010="    AINIT: IN std_logic);"text011="end component;"text012=""text013=""text014=""text015="-- Synplicity black box declaration"text016="attribute black_box : boolean;"text017="attribute black_box of tenths: component is true;"text018=""text019=" "text020="-------------------------------------------------------------"text021=" "text022="-- The following code must appear in the VHDL architecture body."text023="-- Substitute your own instance name and net names."text024=" "text025="your_instance_name : tenths"text026="        port map ("text027="            Q => Q,"text028="            CLK => CLK,"text029="            Q_THRESH0 => Q_THRESH0,"text030="            CE => CE,"text031="            AINIT => AINIT);"text032=" "[COREGEN.VERILOG Component Instantiation.tenths]type=templatetext000=" "text001=" "text002="// The following must be inserted into your Verilog file for this"text003="// core to be instantiated. Change the instance name and port connections"text004="// (in parentheses) to your own signal names."text005=" "text006="tenths YourInstanceName ("text007="    .Q(Q),"text008="    .CLK(CLK),"text009="    .Q_THRESH0(Q_THRESH0),"text010="    .CE(CE),"text011="    .AINIT(AINIT));"text012=""text013=" "