Release 6.2i Map G.30Xilinx Mapping Report File for Design 'top'Design Information------------------Command Line   : C:/eda/Xilinx/bin/nt/map.exe -intstyle ise -p xc2v500-fg256-6
-cm area -gf
D:\CD\Example-8-2\Incremental_design\Incremental_demo\top_map_guide.ncd -gm
incremental -pr b -k 4 -c 100 -tx off -o top_map.ncd top.ngd top.pcf Target Device  : x2v500Target Package : fg256Target Speed   : -6Mapper Version : virtex2 -- $Revision: 1.16.8.1 $Mapped Date    : Wed Jun 02 03:27:19 2004Design Summary--------------Number of errors:      0Number of warnings:    1Logic Utilization:  Number of Slice Flip Flops:          14 out of   6,144    1%  Number of 4 input LUTs:               7 out of   6,144    1%Logic Distribution:  Number of occupied Slices:           15 out of   3,072    1%  Number of Slices containing only related logic:      15 out of      15  100%  Number of Slices containing unrelated logic:          0 out of      15    0%        *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs:              7 out of   6,144    1%  Number of bonded IOBs:               15 out of     172    8%    IOB Flip Flops:                    10  Number of GCLKs:                      4 out of      16   25%  Number of DCMs:                       1 out of       8   12%Total equivalent gate count for design:  7,249Additional JTAG gate count for IOBs:  720Peak Memory Usage:  81 MBNOTES:   Related logic is defined as being logic that shares connectivity -   e.g. two LUTs are "related" if they share common inputs.   When assembling slices, Map gives priority to combine logic that   is related.  Doing so results in the best timing performance.   Unrelated logic shares no connectivity.  Map will only begin   packing unrelated logic into a slice once 99% of the slices are   occupied through related logic packing.   Note that once logic distribution reaches the 99% level through   related logic packing, this does not mean the device is completely   utilized.  Unrelated logic packing will then begin, continuing until   all usable LUTs and FFs are occupied.  Depending on your timing   budget, increased levels of unrelated logic packing may adversely   affect the overall timing performance of your design.Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group SummarySection 10 - Modular Design SummarySection 11 - Timing ReportSection 12 - Configuration String InformationSection 13 - Additional Device Resource CountsSection 1 - Errors------------------Section 2 - Warnings--------------------WARNING:MapLib:643 - Guide file
   D:\CD\Example-8-2\Incremental_design\Incremental_demo\top_map_guide.ngm was
   not created using -gm incremental.  This means that logic optimization and
   packing across Area Group boundaries was allowed when this guide file was
   created.  These optimizations will be prevented during this implementation
   and may cause unchanged Area Groups to be re-implemented.Section 3 - Informational-------------------------INFO:LIT:95 - All of the external outputs in this design are using slew rate
   limited output drivers. The delay on speed critical outputs can be
   dramatically reduced by designating them as fast outputs in the schematic.INFO:MapLib:562 - No environment variables are currently set.INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
   Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:   BUFGP symbol "bufg_moda" (output signal=moda_clk),   BUFGP symbol "bufg_modb" (output signal=modb_clk),   BUFGP symbol "bufg_modc" (output signal=modc_clk),   BUFG symbol "globalclk" (output signal=clk_top)INFO:Pack:1553 - The register instance_a/MODA_OUT is packed into an I/O
   component. The I/O packing occurs exceeding area group AG_instance_a
   boundary.INFO:Pack:1553 - The register instance_a/Q0_OUT is packed into an I/O component.
   The I/O packing occurs exceeding area group AG_instance_a boundary.INFO:Pack:1553 - The register instance_b/MODB_OUT is packed into an I/O
   component. The I/O packing occurs exceeding area group AG_instance_b
   boundary.INFO:Pack:1553 - The register instance_b/Q0_OUT is packed into an I/O component.
   The I/O packing occurs exceeding area group AG_instance_b boundary.INFO:Pack:1553 - The register instance_c/C2TOP_OUT is packed into an I/O
   component. The I/O packing occurs exceeding area group AG_instance_c
   boundary.INFO:Pack:1553 - The register instance_a/A2TOP_OBUFT_I_OUT is packed into an I/O
   component. The I/O packing occurs exceeding area group AG_instance_a
   boundary.INFO:Pack:1553 - The register instance_c/MODC_OUT is packed into an I/O
   component. The I/O packing occurs exceeding area group AG_instance_c
   boundary.INFO:Pack:1553 - The register instance_c/Q0_OUT is packed into an I/O component.
   The I/O packing occurs exceeding area group AG_instance_c boundary.INFO:Pack:1553 - The register instance_b/Q2_OUT is packed into an I/O component.
   The I/O packing occurs exceeding area group AG_instance_b boundary.INFO:Pack:1553 - The register instance_c/Q2_OUT is packed into an I/O component.
   The I/O packing occurs exceeding area group AG_instance_c boundary.Section 4 - Removed Logic Summary---------------------------------Section 5 - Removed Logic-------------------------To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.Section 6 - IOB Properties--------------------------+------------------------------------------------------------------------------------------------------------------------+| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   ||                                    |         |           |             | Strength | Rate |          |          | Delay |+------------------------------------------------------------------------------------------------------------------------+| dll_rst                            | IOB     | INPUT     | LVTTL       |          |      |          |          |       || ipad_dll_clk_in                    | IOB     | INPUT     | LVTTL       |          |      |          |          |       || mod_c_out                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OFF1     |          |       || moda_clk_pad                       | IOB     | INPUT     | LVTTL       |          |      |          |          |       || moda_data                          | IOB     | INPUT     | LVTTL       |          |      | INFF1    |          |       || moda_out                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OFF1     |          |       || modb_clk_pad                       | IOB     | INPUT     | LVTTL       |          |      |          |          |       || modb_data                          | IOB     | INPUT     | LVTTL       |          |      | INFF1    |          |       || modb_out                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OFF1     |          |       || modc_clk_pad                       | IOB     | INPUT     | LVTTL       |          |      |          |          |       || modc_data                          | IOB     | INPUT     | LVTTL       |          |      | INFF1    |          |       || modc_out                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OFF1     |          |       || obuft_out                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OFF1     |          |       || top2a_c                            | IOB     | INPUT     | LVTTL       |          |      | INFF1    |          |       || top2b                              | IOB     | INPUT     | LVTTL       |          |      | INFF1    |          |       |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------NCD slice b2c was NOT guided.NCD slice instance_b/Q3_OUT was NOT guided.  Guided Mapping Summary Info  ---------------------------  Total number of slices in guide NCDs = 14.  Total number of guided slices = 12.  85.7 % of guide NCD slices were guided.Section 9 - Area Group Summary------------------------------AREA_GROUP AG_instance_a  RANGE: SLICE_X32Y59:SLICE_X45Y42  No COMPRESSION specified for AREA_GROUP AG_instance_a  AREA_GROUP Logic Utilization:  Number of Slice Flip Flops:     5 out of    504    1%  Logic Distribution:    Number of occupied Slices:                             5 out of    252    1%    Number Slices used containing only related logic:      5 out of      5  100%  Total Number 4 input LUTs:      2 out of    504    1%      Number used as logic:                     2AREA_GROUP AG_instance_b  RANGE: SLICE_X16Y59:SLICE_X29Y42  No COMPRESSION specified for AREA_GROUP AG_instance_b  The following change(s) were detected in this AREA_GROUP:  A logic change was detected.  AREA_GROUP will be re-implemented due to this change.  AREA_GROUP Logic Utilization:  Number of Slice Flip Flops:     5 out of    504    1%  Logic Distribution:    Number of occupied Slices:                             5 out of    252    1%    Number Slices used containing only related logic:      5 out of      5  100%  Total Number 4 input LUTs:      2 out of    504    1%      Number used as logic:                     2AREA_GROUP AG_instance_c  RANGE: SLICE_X0Y59:SLICE_X13Y42  No COMPRESSION specified for AREA_GROUP AG_instance_c  AREA_GROUP Logic Utilization:  Number of Slice Flip Flops:     4 out of    504    1%  Logic Distribution:    Number of occupied Slices:                             4 out of    252    1%    Number Slices used containing only related logic:      4 out of      4  100%  Total Number 4 input LUTs:      2 out of    504    1%      Number used as logic:                     2Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------This design was not run using timing mode.Section 12 - Configuration String Details-----------------------------------------Use the "-detail" map option to print out Configuration StringsSection 13 - Additional Device Resource Counts----------------------------------------------Number of JTAG Gates for IOBs = 15Number of Equivalent Gates for Design = 7,249Number of RPM Macros = 0Number of Hard Macros = 0CAPTUREs = 0BSCANs = 0STARTUPs = 0PCILOGICs = 0DCMs = 1GCLKs = 4ICAPs = 018X18 Multipliers = 0Block RAMs = 0TBUFs = 0Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 11IOB Dual-Rate Flops not driven by LUTs = 0IOB Dual-Rate Flops = 0IOB Slave Pads = 0IOB Master Pads = 0IOB Latches not driven by LUTs = 0IOB Latches = 0IOB Flip Flops not driven by LUTs = 5IOB Flip Flops = 10Unbonded IOBs = 0Bonded IOBs = 15Total Shift Registers = 0Static Shift Registers = 0Dynamic Shift Registers = 016x1 ROMs = 016x1 RAMs = 032x1 RAMs = 0Dual Port RAMs = 0MUXFs = 0MULT_ANDs = 04 input LUTs used as Route-Thrus = 04 input LUTs = 7Slice Latches not driven by LUTs = 0Slice Latches = 0Slice Flip Flops not driven by LUTs = 6Slice Flip Flops = 14Slices = 15Number of LUT signals with 4 loads = 0Number of LUT signals with 3 loads = 0Number of LUT signals with 2 loads = 6Number of LUT signals with 1 load = 1NGM Average fanout of LUT = 1.86NGM Maximum fanout of LUT = 2NGM Average fanin for LUT = 2.8571Number of LUT symbols = 7Number of IPAD symbols = 10Number of IBUF symbols = 10Number of DCM symbols = 1