--This file is for Synplify/Synplify Pro to declare the Xilinx Virtex2 primitives as black box.
library IEEE;
use IEEE.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
entity PULLUP is
 port (
   O : out std_logic
 );
 attribute syn_not_a_driver : boolean;
 attribute syn_not_a_driver of O : signal is true;
end entity PULLUP;

architecture bb of PULLUP is
attribute syn_black_box of bb : architecture is true;
attribute syn_noprune of bb : architecture is true;
begin
end architecture bb;

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
entity PULLDOWN is
 port (
   O : out std_logic
 );
 attribute syn_not_a_driver : boolean;
 attribute syn_not_a_driver of O : signal is true;
end entity PULLDOWN;

architecture bb of PULLDOWN is
attribute syn_black_box of bb : architecture is true;
attribute syn_noprune of bb : architecture is true;
begin
end architecture bb;

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
entity LUT1 is
 generic (INIT : bit_vector(1 downto 0));
 port (
   O : out std_logic;
   I0 : in std_logic
 );
end entity LUT1;

architecture lut of LUT1 is
attribute xc_map of lut : architecture is "lut";
begin
O <= To_StdULogic(INIT(1)) when I0 = '1' else To_StdULogic(INIT(0));
end architecture lut;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library synplify;
use synplify.attributes.all;
entity LUT2 is
 generic (INIT : bit_vector(3 downto 0));
 port (
   O : out std_logic;
  I0 : in std_logic;
  I1 : in std_logic
 );
end entity LUT2;

architecture lut of LUT2 is
attribute xc_map of lut : architecture is "lut";
signal b : std_logic_vector(1 downto 0);
signal tmp : integer range 0 to 7;
begin
   b <= (I1, I0);
   tmp <= conv_integer(b);
   O <= To_StdULogic(INIT(tmp));
end architecture lut;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library synplify;
use synplify.attributes.all;
entity LUT3 is
 generic (INIT : bit_vector(7 downto 0));
 port (
   O : out std_logic;
  I0 : in std_logic;
  I1 : in std_logic;
  I2 : in std_logic
 );
end entity LUT3;

architecture lut of LUT3 is
attribute xc_map of lut : architecture is "lut";
signal b : std_logic_vector(2 downto 0);
signal tmp : integer range 0 to 7;
begin
   b <= (I2, I1, I0);
   tmp <= conv_integer(b);
   O <= To_StdULogic(INIT(tmp));
end architecture lut;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library synplify;
use synplify.attributes.all;
entity LUT4 is
 generic (INIT : bit_vector(15 downto 0));
 port (
   O : out std_logic;
  I0 : in std_logic;
  I1 : in std_logic;
  I2 : in std_logic;
  I3 : in std_logic
  );
end entity LUT4;

architecture lut of LUT4 is
attribute xc_map of lut : architecture is "lut";
signal b : std_logic_vector(3 downto 0);
signal tmp : integer range 0 to 15;
begin
  b <= (I3, I2, I1, I0);
  tmp <= conv_integer(b);
  O <= To_StdUlogic(INIT(tmp));
end architecture lut;

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
package components is
   attribute syn_black_box of components : package is true;
   attribute syn_noprune : boolean;
component BSCAN_VIRTEX2
 port (
   TDO1 : in std_logic;
   TDO2 : in std_logic;
   CAPTURE : out std_logic;
   DRCK1 : out std_logic;
   DRCK2 : out std_logic;
   RESET : out std_logic;
   SEL1 : out std_logic;
   SEL2 : out std_logic;
   SHIFT : out std_logic;
   TDI : out std_logic;
   UPDATE : out std_logic
 );
end component;
attribute syn_black_box of BSCAN_VIRTEX2 : component is true;
component BUF
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of BUF : component is true;
component BUFCF
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of BUFCF : component is true;
component BUFE
 port (
   O : out std_logic;
   E : in std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of BUFE : component is true;
attribute black_box_tri_pins of BUFE : component is "O";
component BUFG
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of BUFG : component is true;
component BUFGDLL
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of BUFGDLL : component is true;
component BUFGCE
 port (
   O  : out std_logic;
   CE : in std_logic;
   I  : in std_logic
 );
end component;
attribute syn_black_box of BUFGCE : component is true;
component BUFGCE_1
 port (
   O  : out std_logic;
   CE : in std_logic;
   I  : in std_logic
 );
end component;
attribute syn_black_box of BUFGCE_1 : component is true;
component BUFGMUX
 port (
   O  : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   S  : in std_logic
 );
end component;
attribute syn_black_box of BUFGMUX : component is true;
component BUFGMUX_1
 port (
   O  : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   S  : in std_logic
 );
end component;
attribute syn_black_box of BUFGMUX_1 : component is true;
component BUFGP
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of BUFGP : component is true;
component BUFT
 port (
   O : out std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of BUFT : component is true;
attribute black_box_tri_pins of BUFT : component is "O";
component CAPTURE_VIRTEX2
 port (
   CAP : in std_logic;
   CLK : in std_logic
 );
end component;
attribute syn_black_box of CAPTURE_VIRTEX2 : component is true;
attribute syn_noprune of CAPTURE_VIRTEX2 : component is true;
component CLKDLL
 port (
   CLK0 : out std_logic;
   CLK90 : out std_logic;
   CLK180 : out std_logic;
   CLK270 : out std_logic;
   CLK2X : out std_logic;
   CLKDV : out std_logic;
   LOCKED : out std_logic;
   CLKIN : in std_logic;
   CLKFB : in std_logic;
   RST : in std_logic
 );
end component;
attribute syn_black_box of CLKDLL : component is true;
component CLKDLLE
 port (
   CLK0 : out std_logic;
   CLK90 : out std_logic;
   CLK180 : out std_logic;
   CLK270 : out std_logic;
   CLK2X : out std_logic;
   CLK2X180 : out std_logic;
   CLKDV : out std_logic;
   LOCKED : out std_logic;
   CLKIN : in std_logic;
   CLKFB : in std_logic;
   RST : in std_logic
 );
end component;
attribute syn_black_box of CLKDLLE : component is true;
component CLKDLLHF
 port (
   CLK0 : out std_logic;
   CLK180 : out std_logic;
   CLKDV : out std_logic;
   LOCKED : out std_logic;
   CLKIN : in std_logic;
   CLKFB : in std_logic;
   RST : in std_logic
 );
end component;
attribute syn_black_box of CLKDLLHF : component is true;
component DCM
    generic (DFS_FREQUENCY_MODE : string := "LOW";
             DLL_FREQUENCY_MODE : string := "LOW";
             DUTY_CYCLE_CORRECTION : boolean := TRUE;
             CLKIN_DIVIDE_BY_2 : boolean := FALSE;
             CLK_FEEDBACK : string := "1X";
             CLKOUT_PHASE_SHIFT : string := "NONE";
             FACTORY_JF : bit_vector := X"00";
             STARTUP_WAIT : boolean := FALSE;
	     DSS_MODE	  : string := "NONE";
             PHASE_SHIFT  : integer := 0 ;
             CLKFX_MULTIPLY : integer  := 4 ;
	     CLKFX_DIVIDE : integer  := 1;
             CLKDV_DIVIDE : real := 2.0;
             DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"
             ); 
 port ( CLKIN : in std_logic;
	    CLKFB : in std_logic;
	    DSSEN : in std_logic;
	    PSINCDEC : in std_logic;
	    PSEN : in std_logic;
	    PSCLK : in std_logic;
	    RST : in std_logic;
	    CLK0 : out std_logic;
        CLK90 : out std_logic;
        CLK180 : out std_logic;
	    CLK270 : out std_logic;
        CLK2X : out std_logic;
        CLK2X180 : out std_logic;
	    CLKDV : out std_logic;
	    CLKFX : out std_logic;
	    CLKFX180 : out std_logic;
	    LOCKED : out std_logic;
	    PSDONE : out std_logic;
	    STATUS : out std_logic_vector(7 downto 0)
 );
end component;
attribute syn_black_box of DCM : component is true;
component FD
 port (
   Q : out std_logic;
   C : in std_logic;
   D : in std_logic
 );
end component;
attribute syn_black_box of FD : component is true;
component FDC
 port (
   Q : out std_logic;
   C : in std_logic;
   CLR : in std_logic;
   D : in std_logic
 );
end component;
attribute syn_black_box of FDC : component is true;
component FDCE
 port (
   Q : out std_logic;
   C : in std_logic;
   CE : in std_logic;
   CLR : in std_logic;
   D : in std_logic
 );
end component;
attribute syn_black_box of FDCE : component is true;
component FDCE_1
 port (
   Q : out std_logic;
   C : in std_logic;
   CE : in std_logic;
   CLR : in std_logic;
   D : in std_logic
 );
end component;
attribute syn_black_box of FDCE_1 : component is true;
component FDCP
 port (
   Q : out std_logic;
   C : in std_logic;
   CLR : in std_logic;
   D : in std_logic;
   PRE : in std_logic
 );
end component;
attribute syn_black_box of FDCP : component is true;
component FDCPE
 port (
   Q : out std_logic;
   C : in std_logic;
   CE : in std_logic;
   CLR : in std_logic;
   D : in std_logic;
   PRE : in std_logic
 );
end component;
attribute syn_black_box of FDCPE : component is true;
component FDCPE_1
 port (
   Q : out std_logic;
   C : in std_logic;
   CE : in std_logic;
   CLR : in std_logic;
   D : in std_logic;
   PRE : in std_logic
 );
end component;
attribute syn_black_box of FDCPE_1 : component is true;
component FDCP_1
 port (
   Q : out std_logic;
   C : in std_logic;
   CLR : in std_logic;
   D : in std_logic;
   PRE : in std_logic
 );
end component;
attribute syn_black_box of FDCP_1 : component is true;
component FDC_1
 port (
   Q : out std_logic;
   C : in std_logic;
   CLR : in std_logic;
   D : in std_logic
 );
end component;
attribute syn_black_box of FDC_1 : component is true;
component FDDRCPE
 port (
   Q : out std_logic;
   C0 : in std_logic;
   C1 : in std_logic;
   CE : in std_logic;
   CLR : in std_logic;
   D0 : in std_logic;
   D1 : in std_logic;
   PRE : in std_logic
 );
end component;
attribute syn_black_box of FDDRCPE : component is true;
component FDDRRSE
 port (
   Q : out std_logic;
   C0 : in std_logic;
   C1 : in std_logic;
   CE : in std_logic;
   D0 : in std_logic;
   D1 : in std_logic;
   R : in std_logic;
   S : in std_logic
 );
end component;
attribute syn_black_box of FDDRRSE : component is true;
component FDE
 port (
   Q : out std_logic;
   C : in std_logic;
   CE : in std_logic;
   D : in std_logic
 );
end component;
attribute syn_black_box of FDE : component is true;
component FDE_1
 port (
   Q : out std_logic;
   C : in std_logic;
   CE : in std_logic;
   D : in std_logic
 );
end component;
attribute syn_black_box of FDE_1 : component is true;
component FDP
 port (
   Q : out std_logic;
   C : in std_logic;
   D : in std_logic;
   PRE : in std_logic
 );
end component;
attribute syn_black_box of FDP : component is true;
component FDPE
 port (
   Q : out std_logic;
   C : in std_logic;
   CE : in std_logic;
   D : in std_logic;
   PRE : in std_logic
 );
end component;
attribute syn_black_box of FDPE : component is true;
component FDPE_1
 port (
   Q : out std_logic;
   C : in std_logic;
   CE : in std_logic;
   D : in std_logic;
   PRE : in std_logic
 );
end component;
attribute syn_black_box of FDPE_1 : component is true;
component FDP_1
 port (
   Q : out std_logic;
   C : in std_logic;
   D : in std_logic;
   PRE : in std_logic
 );
end component;
attribute syn_black_box of FDP_1 : component is true;
component FDR
 port (
   Q : out std_logic;
   C : in std_logic;
   D : in std_logic;
   R : in std_logic
 );
end component;
attribute syn_black_box of FDR : component is true;
component FDRE
 port (
   Q : out std_logic;
   C : in std_logic;
   CE : in std_logic;
   D : in std_logic;
   R : in std_logic
 );
end component;
attribute syn_black_box of FDRE : component is true;
component FDRE_1
 port (
   Q : out std_logic;
   C : in std_logic;
   CE : in std_logic;
   D : in std_logic;
   R : in std_logic
 );
end component;
attribute syn_black_box of FDRE_1 : component is true;
component FDRS
 port (
   Q : out std_logic;
   C : in std_logic;
   D : in std_logic;
   R : in std_logic;
   S : in std_logic
 );
end component;
attribute syn_black_box of FDRS : component is true;
component FDRSE
 port (
   Q : out std_logic;
   C : in std_logic;
   CE : in std_logic;
   D : in std_logic;
   R : in std_logic;
   S : in std_logic
 );
end component;
attribute syn_black_box of FDRSE : component is true;
component FDRSE_1
 port (
   Q : out std_logic;
   C : in std_logic;
   CE : in std_logic;
   D : in std_logic;
   R : in std_logic;
   S : in std_logic