?? module_c.v
字號:
module module_c (CLK_TOP,TOP2A_C_IN,B2C_IN,A2C_IN,
MODC_DATA,MODC_CLK,MODC_OUT,
C2TOP_OUT,C2AND2_OUT,C2A_OUT);
input CLK_TOP ;
input B2C_IN ;
input TOP2A_C_IN ;
input A2C_IN ;
input MODC_DATA, MODC_CLK;
output MODC_OUT;
output C2AND2_OUT ;
output C2A_OUT ;
output C2TOP_OUT ;
// add your declarations here
reg Q0_OUT, Q1_OUT, Q2_OUT, Q3_OUT ;
reg C2AND2_OUT, C2A_OUT, C2TOP_OUT ;
reg MODC_OUT;
wire AND4_OUT ;
wire OR4_OUT ;
// add your code here
assign AND4_OUT = Q0_OUT && Q1_OUT && Q2_OUT && Q3_OUT ;
assign OR4_OUT = Q0_OUT || Q1_OUT || Q2_OUT || Q3_OUT ;
always @ (posedge CLK_TOP)
begin : TOP_CLK
Q0_OUT <= MODC_DATA ;
Q2_OUT <= TOP2A_C_IN ;
MODC_OUT <= OR4_OUT ;
C2AND2_OUT <= AND4_OUT ;
end
always @ (posedge MODC_CLK)
begin : CLK_MODA
Q1_OUT <= B2C_IN ;
Q3_OUT <= A2C_IN ;
C2A_OUT <= AND4_OUT ;
C2TOP_OUT <= OR4_OUT ;
end
endmodule
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