#
#
#
# Created by Synplify Verilog HDL Compiler version 7.2, Build 112R from Synplicity, Inc.
# Copyright 1994-1999 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Wed Mar 26 20:29:46 2003
#
#
#OPTIONS:"|-ram|-primux|-fixsmult|-sdff_counter|-infer_seqShift|-IJ:\\eda\\synplicity\\Synplify_72\\lib|-v2001|-autosm|-fid2|-sharing|on|-encrypt|-ui"
#CUR:"J:\\eda\\synplicity\\Synplify_72\\bin\\c_ver.exe":1035360168l
#CUR:"J:\\Example-8-1\\Modular_Design\\syn_modules\\module_a\\module_a.v":1048670595l
f "J:\Example-8-1\Modular_Design\syn_modules\module_a\module_a.v"; # file 0
@E@MR@4j::4(::R4cI	FsR8lFk_DCNCRPsFHDoN;
PHR3#sPCHoDFR
4;N3PRFosHhCNlRF"l8CkD_;N"
@HR@dj::dn::R4.B_piaRmuB_pia;mu
@HR@cj::cn::R44A_.qQAhR.Qq_h
;

@HR@6j::6n::R4da.muqh_QRuam.Qq_h
;

@HR@nj::nn::R44B_.qQBhR.Qq_h
;

@HR@(j::(n::R4cvqm7_a7qqmRv77q_q;aq
@HR@(j:::4((c:.R7vmqp_BimRv7Bq_p
i;
@FR@Uj::U(::R4cvqm7_amzR7vmqz_ma
;

@FR@gj::g(::R4dq_.AmRzaq_.Am;za
@FR@4j:j::(4.j:d.Rqa_mumwAza__QmRzaqm.auA_mz_waQz_ma
;

@FR@4j:4::(444:d.RqBz_ma.RqBz_mab;
Rj@@:44::.4:Rk0sCsR0k0CRs;kC
@bR@4j::44::V.RNCD#RDVN#VCRNCD#;R
b@:@j.j4:::.46VR8VjRT_amzR_TjmRzavqm7_a7qqpRBim_aub;
Rj@@::.4j4:.:86RVTVR.z_ma.RT_amzRuam.Qq_hpRBim_aub;
Rj@@::.UjU:.:86RVTVR4z_ma4RT_amzRqA._RQhvqm7_iBp;R
b@:@j.jU:::.U6VR8VdRT_amzR_TdmRzaB_.qQvhRm_7qB;pi
@bR@4j:gU:4::4g6NcRMR8Pqch7_amzR7qhcz_ma.RT_amzR_TjmRzaTm4_zTaRdz_mab;
Rj@@::.j4.(:jd:6RPFsRcm)_amzRcm)_amzR_T.mRzaTmj_zTaR4z_madRT_amz;R
b@:@j.j4:::.46VR8V.RqAz_ma.RqAz_mahRq7mc_zBaRpai_m
u;b@R@j4:.:.j:4R:68RVVvqm7_amzR7vmqz_ma)Rmcz_mapRBim_aub;
Rj@@::.UjU:.:86RVqVR.mB_zqaR.mB_zmaR)mc_zvaRm_7qB;pi
@bR@.j:U::j.6U:RV8VRaq.mmu_Aazw_mQ_zqaR.uam_zmAwQa__amzR7qhcz_mamRv7Bq_p
i;C
;