Release 5.2i - xst F.28Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.--> Parameter TMPDIR set to __projnavCPU : 0.00 / 0.67 s | Elapsed : 0.00 / 1.00 s --> Reading design: module_b.prjTABLE OF CONTENTS  1) Synthesis Options Summary  2) HDL Compilation  3) HDL Analysis  4) HDL Synthesis     4.1) HDL Synthesis Report  5) Low Level Synthesis  6) Final Report     6.1) Device utilization summary     6.2) TIMING REPORT=========================================================================*                      Synthesis Options Summary                        *=========================================================================---- Source ParametersInput File Name                    : module_b.prjInput Format                       : VERILOGIgnore Synthesis Constraint File   : NOVerilog Search Path                : Verilog Include Directory          : ---- Target ParametersOutput File Name                   : module_bOutput Format                      : NGCTarget Device                      : xc2v40-5cs144---- Source OptionsTop Module Name                    : module_bAutomatic FSM Extraction           : YESFSM Encoding Algorithm             : AutoRAM Extraction                     : YesRAM Style                          : AutoROM Extraction                     : YesROM Style                          : AutoMux Extraction                     : YESMux Style                          : AutoDecoder Extraction                 : YESPriority Encoder Extraction        : YESShift Register Extraction          : YESLogical Shifter Extraction         : YESXOR Collapsing                     : YESResource Sharing                   : YESComplex Clock Enable Extraction    : YESMultiplier Style                   : autoAutomatic Register Balancing       : No---- Target OptionsAdd IO Buffers                     : NOGlobal Maximum Fanout              : 500Add Generic Clock Buffer(BUFG)     : 16Register Duplication               : YESEquivalent register Removal        : YESSlice Packing                      : YESPack IO Registers into IOBs        : false---- General OptionsOptimization Criterion             : SpeedOptimization Effort                : 1Keep Hierarchy                     : NOGlobal Optimization                : AllClockNetsRTL Output                         : YesWrite Timing Constraints           : NOHierarchy Separator                : _Bus Delimiter                      : <>Case Specifier                     : maintainTop module area constraint         : 100Top module allowed area overflow   : 5---- Other Optionsread_cores                         : YEScross_clock_analysis               : NOverilog2001                        : YES==================================================================================================================================================*                          HDL Compilation                              *=========================================================================Compiling source file "module_b.prj"Compiling include file "../module_b.v"Module <module_b> compiledCompiling include file "J:/eda/Xilinx/verilog/src/iSE/unisim_comp.v"No errors in compilation=========================================================================*                            HDL Analysis                               *=========================================================================Analysis of file <module_b.prj> succeeded.  Analyzing top module <module_b>.Module <module_b> is correct for synthesis.=========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <module_b>.    Related source file is ../module_b.v.    Found 1-bit register for signal <B2C_OUT>.    Found 1-bit register for signal <B2TOP_OBUFT_T_OUT>.    Found 1-bit register for signal <B2A_OUT>.    Found 1-bit register for signal <MODB_OUT>.    Found 1-bit register for signal <Q0_OUT>.    Found 1-bit register for signal <Q1_OUT>.    Found 1-bit register for signal <Q2_OUT>.    Found 1-bit register for signal <Q3_OUT>.    Summary:	inferred   8 D-type flip-flop(s).Unit <module_b> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# Registers                        : 8  1-bit register                   : 8==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================Library "J:/eda/Xilinx/data/librtl.xst" ConsultedOptimizing unit <module_b> ...Mapping all equations...Loading device for application Xst from file '2v40.nph' in environment J:/eda/Xilinx.Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block module_b, actual ratio is 1.=========================================================================*                            Final Report                               *=========================================================================Final ResultsRTL Top Level Output File Name     : module_b.ngrTop Level Output File Name         : module_bOutput Format                      : NGCOptimization Criterion             : SpeedKeep Hierarchy                     : NOMacro Generator                    : macro+Design Statistics# IOs                              : 10Macro Statistics :# Registers                        : 8#      1-bit register              : 8Cell Usage :# BELS                             : 2#      LUT4_D                      : 2# FlipFlops/Latches                : 8#      FD                          : 8=========================================================================Device utilization summary:---------------------------Selected Device : 2v40cs144-5  Number of Slices:                       4  out of    256     1%   Number of Slice Flip Flops:             8  out of    512     1%   Number of 4 input LUTs:                 2  out of    512     0%  =========================================================================TIMING REPORTNOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT      GENERATED AFTER PLACE-and-ROUTE.Clock Information:-----------------------------------------------------+------------------------+-------+Clock Signal                       | Clock buffer(FF name)  | Load  |-----------------------------------+------------------------+-------+CLK_TOP                            | NONE                   | 4     |MODB_CLK                           | NONE                   | 4     |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -5   Minimum period: 1.896ns (Maximum Frequency: 527.426MHz)   Minimum input arrival time before clock: 0.322ns   Maximum output required time after clock: 0.494ns   Maximum combinational path delay: No path foundTiming Detail:--------------All values displayed in nanoseconds (ns)-------------------------------------------------------------------------Timing constraint: Default period analysis for Clock 'CLK_TOP'Delay:               1.896ns (Levels of Logic = 1)  Source:            Q0_OUT  Destination:       B2A_OUT  Source Clock:      CLK_TOP rising  Destination Clock: CLK_TOP rising  Data Path: Q0_OUT to B2A_OUT                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     FD:C->Q               2   0.494   0.698  Q0_OUT (Q0_OUT)     LUT4_D:I0->LO         1   0.382   0.000  AND4_OUT1 (N118)     FD:D                      0.322          B2A_OUT    ----------------------------------------    Total                      1.896ns (1.198ns logic, 0.698ns route)                                       (63.2% logic, 36.8% route)-------------------------------------------------------------------------Timing constraint: Default period analysis for Clock 'MODB_CLK'Delay:               1.896ns (Levels of Logic = 1)  Source:            Q3_OUT  Destination:       B2C_OUT  Source Clock:      MODB_CLK rising  Destination Clock: MODB_CLK rising  Data Path: Q3_OUT to B2C_OUT                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     FD:C->Q               2   0.494   0.698  Q3_OUT (Q3_OUT)     LUT4_D:I1->O          1   0.382   0.000  OR4_OUT1 (OR4_OUT)     FD:D                      0.322          B2C_OUT    ----------------------------------------    Total                      1.896ns (1.198ns logic, 0.698ns route)                                       (63.2% logic, 36.8% route)-------------------------------------------------------------------------Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK_TOP'Offset:              0.322ns (Levels of Logic = 0)  Source:            TOP2B_IN  Destination:       Q2_OUT  Destination Clock: CLK_TOP rising  Data Path: TOP2B_IN to Q2_OUT                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     FD:D                      0.322          Q2_OUT    ----------------------------------------    Total                      0.322ns (0.322ns logic, 0.000ns route)                                       (100.0% logic, 0.0% route)-------------------------------------------------------------------------Timing constraint: Default OFFSET IN BEFORE for Clock 'MODB_CLK'Offset:              0.322ns (Levels of Logic = 0)  Source:            A2B_IN  Destination:       Q1_OUT  Destination Clock: MODB_CLK rising  Data Path: A2B_IN to Q1_OUT                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     FD:D                      0.322          Q1_OUT    ----------------------------------------    Total                      0.322ns (0.322ns logic, 0.000ns route)                                       (100.0% logic, 0.0% route)-------------------------------------------------------------------------Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK_TOP'Offset:              0.494ns (Levels of Logic = 0)  Source:            MODB_OUT  Destination:       MODB_OUT  Source Clock:      CLK_TOP rising  Data Path: MODB_OUT to MODB_OUT                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     FD:C->Q               0   0.494   0.000  MODB_OUT (MODB_OUT)    ----------------------------------------    Total                      0.494ns (0.494ns logic, 0.000ns route)                                       (100.0% logic, 0.0% route)-------------------------------------------------------------------------Timing constraint: Default OFFSET OUT AFTER for Clock 'MODB_CLK'Offset:              0.494ns (Levels of Logic = 0)  Source:            B2TOP_OBUFT_T_OUT  Destination:       B2TOP_OBUFT_T_OUT  Source Clock:      MODB_CLK rising  Data Path: B2TOP_OBUFT_T_OUT to B2TOP_OBUFT_T_OUT                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     FD:C->Q               0   0.494   0.000  B2TOP_OBUFT_T_OUT (B2TOP_OBUFT_T_OUT)    ----------------------------------------    Total                      0.494ns (0.494ns logic, 0.000ns route)                                       (100.0% logic, 0.0% route)=========================================================================CPU : 2.72 / 3.63 s | Elapsed : 3.00 / 4.00 s --> Total memory usage is 68400 kilobytes