set -tmpdir __projnav
run
-ifn module_b.prj
-ifmt VERILOG
-ofn module_b
-ofmt NGC
-p xc2v40-5cs144
-top module_b
-opt_mode Speed
-opt_level 1
-iuc NO
-keep_hierarchy NO
-glob_opt AllClockNets
-rtlview Yes
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator _
-bus_delimiter <>
-case maintain
-slice_utilization_ratio 100
-verilog2001 YES
-vlgpath 
-vlgincdir 
-fsm_extract YES -fsm_encoding Auto
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-rom_style Auto
-mux_extract YES
-mux_style Auto
-decoder_extract YES
-priority_extract YES
-shreg_extract YES
-shift_extract YES
-xor_collapse YES
-resource_sharing YES
-complex_clken YES
-mult_style auto
-iobuf NO
-max_fanout 500
-bufg 16
-register_duplication YES
-equivalent_register_removal YES
-register_balancing No
-slice_packing YES
-iob false
-slice_utilization_ratio_maxmargin 5