Release 5.2i - Map F.28Xilinx Mapping Report File for Design 'top'Design Information------------------Command Line   : map top.ngd Target Device  : 2v40Target Package : cs144Target Speed   : -5Mapper Version : virtex2 -- $Revision: 1.4 $Mapped Date    : Thu Mar 27 16:07:49 2003Design Summary--------------Number of errors:      0Number of warnings:    0Logic Utilization:  Number of Slice Flip Flops:          24 out of     512    4%  Number of 4 input LUTs:               7 out of     512    1%Logic Distribution:    Number of occupied Slices:                           24 out of     256    9%    Number of Slices containing only related logic:      24 out of      24  100%    Number of Slices containing unrelated logic:          0 out of      24    0%        *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs:              7 out of     512    1%   Number of bonded IOBs:              15 out of      88   17%   Number of GCLKs:                     4 out of      16   25%   Number of DCMs:                      1 out of       4   25%Total equivalent gate count for design:  7,249Additional JTAG gate count for IOBs:  720Peak Memory Usage:  59 MBNOTES:   Related logic is defined as being logic that shares connectivity -   e.g. two LUTs are "related" if they share common inputs.   When assembling slices, Map gives priority to combine logic that   is related.  Doing so results in the best timing performance.   Unrelated logic shares no connectivity.  Map will only begin   packing unrelated logic into a slice once 99% of the slices are   occupied through related logic packing.   Note that once logic distribution reaches the 99% level through   related logic packing, this does not mean the device is completely   utilized.  Unrelated logic packing will then begin, continuing until   all usable LUTs and FFs are occupied.  Depending on your timing   budget, increased levels of unrelated logic packing may adversely   affect the overall timing performance of your design.Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group SummarySection 10 - Modular Design SummarySection 1 - Errors------------------Section 2 - Warnings--------------------Section 3 - Informational-------------------------INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
   Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:   BUFGP symbol "bufg_moda" (output signal=moda_clk),   BUFGP symbol "bufg_modb" (output signal=modb_clk),   BUFGP symbol "bufg_modc" (output signal=modc_clk),   BUFG symbol "globalclk" (output signal=clk_top)INFO:LIT:95 - All of the external outputs in this design are using slew rate
   limited output drivers. The delay on speed critical outputs can be
   dramatically reduced by designating them as fast outputs in the schematic.Section 4 - Removed Logic Summary---------------------------------Section 5 - Removed Logic-------------------------To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.Section 6 - IOB Properties--------------------------+------------------------------------------------------------------------------------------------------------------------+| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   ||                                    |         |           |             | Strength | Rate |          |          | Delay |+------------------------------------------------------------------------------------------------------------------------+| dll_rst                            | IOB     | INPUT     | LVTTL       |          |      |          |          |       || ipad_dll_clk_in                    | IOB     | INPUT     | LVTTL       |          |      |          |          |       || mod_c_out                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || moda_clk_pad                       | IOB     | INPUT     | LVTTL       |          |      |          |          |       || moda_data                          | IOB     | INPUT     | LVTTL       |          |      |          |          |       || moda_out                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || modb_clk_pad                       | IOB     | INPUT     | LVTTL       |          |      |          |          |       || modb_data                          | IOB     | INPUT     | LVTTL       |          |      |          |          |       || modb_out                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || modc_clk_pad                       | IOB     | INPUT     | LVTTL       |          |      |          |          |       || modc_data                          | IOB     | INPUT     | LVTTL       |          |      |          |          |       || modc_out                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || obuft_out                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || top2a_c                            | IOB     | INPUT     | LVTTL       |          |      |          |          |       || top2b                              | IOB     | INPUT     | LVTTL       |          |      |          |          |       |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------  Guided Mapping Summary Info  ---------------------------  Total number of slices in guide NCDs = 26.  Total number of guided slices = 26.  100.0% of guide NCD slices were guided.  Breakdown for each guide NCD  ----------------------------  Total number of slices in guide NCD
'\example-8-1\modular_design\pims/module_a/module_a.ncd' = 9.  Total number of slices that were guided = 9.  100.0% of guide NCD slices were guided.  Total number of slices in guide NCD
'\example-8-1\modular_design\pims/module_b/module_b.ncd' = 8.  Total number of slices that were guided = 8.  100.0% of guide NCD slices were guided.  Total number of slices in guide NCD
'\example-8-1\modular_design\pims/module_c/module_c.ncd' = 9.  Total number of slices that were guided = 9.  100.0% of guide NCD slices were guided.Section 9 - Area Group Summary------------------------------AREA_GROUP AG_instance_a  RANGE: SLICE_X2Y15:SLICE_X3Y2  RANGE: RAMB16_X1Y1:RAMB16_X0Y1  No COMPRESSION specified for AREA_GROUP AG_instance_a  AREA_GROUP Logic Utilization:  Number of Slice Flip Flops:     8 out of     56   14%  Logic Distribution:    Number of occupied Slices:                           8 out of     28   28%    Number of Slices containing only related logic:      8 out of      8  100%  Total Number 4 input LUTs:      2 out of     56    3%      Number used as logic:                     2AREA_GROUP AG_instance_b  RANGE: SLICE_X8Y15:SLICE_X9Y2  RANGE: RAMB16_X1Y1:RAMB16_X0Y1  No COMPRESSION specified for AREA_GROUP AG_instance_b  AREA_GROUP Logic Utilization:  Number of Slice Flip Flops:     8 out of     56   14%  Logic Distribution:    Number of occupied Slices:                           7 out of     28   25%    Number of Slices containing only related logic:      7 out of      7  100%  Total Number 4 input LUTs:      2 out of     56    3%      Number used as logic:                     2AREA_GROUP AG_instance_c  RANGE: SLICE_X4Y15:SLICE_X5Y2  RANGE: RAMB16_X0Y1:RAMB16_X0Y1  No COMPRESSION specified for AREA_GROUP AG_instance_c  AREA_GROUP Logic Utilization:  Number of Slice Flip Flops:     8 out of     56   14%  Logic Distribution:    Number of occupied Slices:                           8 out of     28   28%    Number of Slices containing only related logic:      8 out of      8  100%  Total Number 4 input LUTs:      2 out of     56    3%      Number used as logic:                     2Section 10 - Modular Design Summary-----------------------------------Modular Design modules successfully assembled.