?? c8051f320.h
字號:
sfr PCA0CPH3 = 0xEE; /* PCA0 MODULE 3 CAPTURE/COMPARE REGISTER HIGH BYTE */
sfr RSTSRC = 0xEF; /* RESET SOURCE */
sfr B = 0xF0; /* B REGISTER */
sfr P0MDIN = 0xF1; /* PORT 0 INPUT MODE REGISTER */
sfr P1MDIN = 0xF2; /* PORT 1 INPUT MODE REGISTER */
sfr P2MDIN = 0xF3; /* PORT 2 INPUT MODE REGISTER */
sfr P3MDIN = 0xF4; /* PORT 3 INPUT MODE REGISTER */
sfr EIP1 = 0xF6; /* EXTENDED INTERRUPT PRIORITY 1 */
sfr EIP2 = 0xF7; /* EXTENDED INTERRUPT PRIORITY 2 */
sfr SPI0CN = 0xF8; /* SPI0 CONTROL */
sfr PCA0L = 0xF9; /* PCA0 COUNTER REGISTER LOW BYTE */
sfr PCA0H = 0xFA; /* PCA0 COUNTER REGISTER HIGH BYTE */
sfr PCA0CPL0 = 0xFB; /* PCA MODULE 0 CAPTURE/COMPARE REGISTER LOW BYTE */
sfr PCA0CPH0 = 0xFC; /* PCA MODULE 0 CAPTURE/COMPARE REGISTER HIGH BYTE */
sfr PCA0CPL4 = 0xFD; /* PCA MODULE 4 CAPTURE/COMPARE REGISTER LOW BYTE */
sfr PCA0CPH4 = 0xFE; /* PCA MODULE 4 CAPTURE/COMPARE REGISTER HIGH BYTE */
sfr VDM0CN = 0xFF; /* VDD MONITOR CONTROL */
/* BIT Registers */
/* TCON 0x88 */
sbit IT0 = TCON ^ 0; /* EXT INTERRUPT 0 TYPE */
sbit IE0 = TCON ^ 1; /* EXT INTERRUPT 0 EDGE FLAG */
sbit IT1 = TCON ^ 2; /* EXT INTERRUPT 1 TYPE */
sbit IE1 = TCON ^ 3; /* EXT INTERRUPT 1 EDGE FLAG */
sbit TR0 = TCON ^ 4; /* TIMER 0 ON/OFF CONTROL */
sbit TF0 = TCON ^ 5; /* TIMER 0 OVERFLOW FLAG */
sbit TR1 = TCON ^ 6; /* TIMER 1 ON/OFF CONTROL */
sbit TF1 = TCON ^ 7; /* TIMER 1 OVERFLOW FLAG */
/* SCON0 0x98 */
sbit RI0 = SCON0 ^ 0; /* RECEIVE INTERRUPT FLAG */
sbit TI0 = SCON0 ^ 1; /* TRANSMIT INTERRUPT FLAG */
sbit RB80 = SCON0 ^ 2; /* RECEIVE BIT 8 */
sbit TB80 = SCON0 ^ 3; /* TRANSMIT BIT 8 */
sbit REN0 = SCON0 ^ 4; /* RECEIVE ENABLE */
sbit MCE0 = SCON0 ^ 5; /* MULTIPROCESSOR COMMUNICATION ENABLE */
sbit S0MODE = SCON0 ^ 7; /* SERIAL MODE CONTROL BIT 0 */
/* IE 0xA8 */
sbit EX0 = IE ^ 0; /* EXTERNAL INTERRUPT 0 ENABLE */
sbit ET0 = IE ^ 1; /* TIMER 0 INTERRUPT ENABLE */
sbit EX1 = IE ^ 2; /* EXTERNAL INTERRUPT 1 ENABLE */
sbit ET1 = IE ^ 3; /* TIMER 1 INTERRUPT ENABLE */
sbit ES0 = IE ^ 4; /* UART0 INTERRUPT ENABLE */
sbit ET2 = IE ^ 5; /* TIMER 2 INTERRUPT ENABLE */
sbit ESPI0 = IE ^ 6; /* SPI0 INTERRUPT ENABLE */
sbit EA = IE ^ 7; /* GLOBAL INTERRUPT ENABLE */
/* IP 0xB8 */
sbit PX0 = IP ^ 0; /* EXTERNAL INTERRUPT 0 PRIORITY */
sbit PT0 = IP ^ 1; /* TIMER 0 PRIORITY */
sbit PX1 = IP ^ 2; /* EXTERNAL INTERRUPT 1 PRIORITY */
sbit PT1 = IP ^ 3; /* TIMER 1 PRIORITY */
sbit PS0 = IP ^ 4; /* UART0 PRIORITY */
sbit PT2 = IP ^ 5; /* TIMER 2 PRIORITY */
sbit PSPI0 = IP ^ 6; /* SPI0 INTERRUPT PRIORITY */
/* SMB0CN 0xC0 */
sbit SI = SMB0CN ^ 0; /* SMBUS0 INTERRUPT FLAG */
sbit ACK = SMB0CN ^ 1; /* ACKNOWLEDGE FLAG */
sbit ARBLOST = SMB0CN ^ 2; /* ARBITRATION LOST INDICATOR */
sbit ACKRQ = SMB0CN ^ 3; /* ACKNOWLEDGE REQUEST */
sbit STO = SMB0CN ^ 4; /* STOP FLAG */
sbit STA = SMB0CN ^ 5; /* START FLAG */
sbit TXMODE = SMB0CN ^ 6; /* TRANSMIT MODE INDICATOR */
sbit MASTER = SMB0CN ^ 7; /* MASTER/SLAVE INDICATOR */
/* TMR2CN 0xC8 */
sbit T2XCLK = TMR2CN ^ 0; /* TIMER 2 EXTERNAL CLOCK SELECT */
sbit TR2 = TMR2CN ^ 2; /* TIMER 2 ON/OFF CONTROL */
sbit T2SPLIT = TMR2CN ^ 3; /* TIMER 2 SPLIT MODE ENABLE */
sbit TF2LEN = TMR2CN ^ 5; /* TIMER 2 LOW BYTE INTERRUPT ENABLE */
sbit TF2L = TMR2CN ^ 6; /* TIMER 2 LOW BYTE OVERFLOW FLAG */
sbit TF2H = TMR2CN ^ 7; /* TIMER 2 HIGH BYTE OVERFLOW FLAG */
/* PSW 0xD0 */
sbit P = PSW ^ 0; /* ACCUMULATOR PARITY FLAG */
sbit F1 = PSW ^ 1; /* USER FLAG 1 */
sbit OV = PSW ^ 2; /* OVERFLOW FLAG */
sbit RS0 = PSW ^ 3; /* REGISTER BANK SELECT 0 */
sbit RS1 = PSW ^ 4; /* REGISTER BANK SELECT 1 */
sbit F0 = PSW ^ 5; /* USER FLAG 0 */
sbit AC = PSW ^ 6; /* AUXILIARY CARRY FLAG */
sbit CY = PSW ^ 7; /* CARRY FLAG */
/* PCA0CN 0xD8H */
sbit CCF0 = PCA0CN ^ 0; /* PCA0 MODULE 0 CAPTURE/COMPARE FLAG */
sbit CCF1 = PCA0CN ^ 1; /* PCA0 MODULE 1 CAPTURE/COMPARE FLAG */
sbit CCF2 = PCA0CN ^ 2; /* PCA0 MODULE 2 CAPTURE/COMPARE FLAG */
sbit CCF3 = PCA0CN ^ 3; /* PCA0 MODULE 3 CAPTURE/COMPARE FLAG */
sbit CCF4 = PCA0CN ^ 4; /* PCA0 MODULE 4 CAPTURE/COMPARE FLAG */
sbit CR = PCA0CN ^ 6; /* PCA0 COUNTER RUN CONTROL */
sbit CF = PCA0CN ^ 7; /* PCA0 COUNTER OVERFLOW FLAG */
/* ADC0CN 0xE8H */
sbit AD0CM0 = ADC0CN ^ 0; /* ADC0 CONVERSION MODE SELECT 0 */
sbit AD0CM1 = ADC0CN ^ 1; /* ADC0 CONVERSION MODE SELECT 1 */
sbit AD0CM2 = ADC0CN ^ 2; /* ADC0 CONVERSION MODE SELECT 2 */
sbit AD0WINT = ADC0CN ^ 3; /* ADC0 WINDOW COMPARE INTERRUPT FLAG */
sbit AD0BUSY = ADC0CN ^ 4; /* ADC0 BUSY FLAG */
sbit AD0INT = ADC0CN ^ 5; /* ADC0 CONVERISION COMPLETE INTERRUPT FLAG */
sbit AD0TM = ADC0CN ^ 6; /* ADC0 TRACK MODE */
sbit AD0EN = ADC0CN ^ 7; /* ADC0 ENABLE */
/* SPI0CN 0xF8H */
sbit SPIF = SPI0CN ^ 7; /* SPI 0 INTERRUPT FLAG */
sbit WCOL = SPI0CN ^ 6; /* SPI 0 WRITE COLLISION FLAG */
sbit MODF = SPI0CN ^ 5; /* SPI 0 MODE FAULT FLAG */
sbit RXOVRN = SPI0CN ^ 4; /* SPI 0 RX OVERRUN FLAG */
sbit NSSMD1 = SPI0CN ^ 3; /* SPI 0 SLAVE SELECT MODE 1 */
sbit NSSMD0 = SPI0CN ^ 2; /* SPI 0 SLAVE SELECT MODE 0 */
sbit TXBMT = SPI0CN ^ 1; /* SPI 0 TRANSMIT BUFFER EMPTY */
sbit SPIEN = SPI0CN ^ 0; /* SPI 0 SPI ENABLE */
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