set chan_en 1  }      # Mapping bit to proper position    set data1 [expr 0x0010|[expr $scrmbl << 11]|[expr $data_rev_bit << 10]| \             [expr $pfcs_rev_obyte << 9]|[expr $pfcs_rev_obit << 8]| \             [expr $pfcs_rev_ibit << 7]|[expr $pfcs_crpt_inv << 6]| \             [expr $pfcs_inv << 5]|[expr $pfcs_mode << 3]|[expr $pfcs_ins << 2]| \             [expr $mode << 1]|$chan_en]  # Writing to TXDP Indirect Channel Common and Specific Config Register  admwr $devID 0xE702 $data1    ### 2.2 Setting TXDP Indirect Channel Specific Config Register ###     if {$mode == 0} {      # Set RESERVED_1 to 1    admwr $devID 0xE703 0x8800  } elseif {$mode == 1} {    # Set Abort type with 0x7D7E in HDLC-like mode    admwr $devID 0xE703 0x4100  }          ### 2.3 Setting GFP Payload Header Type (Applicable for GFP mode Only) ###    if {$mode == 0} {    # TYPE_ADCT_DAT[15:13] = PTI[2:0]    # TYPE_ADCT_DAT[12] = PFI    # TYPE_ADCT_DAT[11:8] = EXI[3:0]    # TYPE_ADCT_DAT[7:0] = UPI[7:0]      set pti 0x0	;#000b    set pfi $pfcs_ins ;# 0 (no payload FCS), 1 (have payload FCS)    set exi 0x0 ;#0000b    set upi 0x01 ;#0000 0001b - frame mapped ethernet        # Mapping bit to proper position    set data2 [expr [expr $pti << 13]|[expr $pfi << 12]|[expr $exi << 8]|$upi]        # Write setting to TXDP Indirect Channel GFP Payload Header Type Register    admwr $devID 0xE704 $data2                     }    ### 2.4 Activiating channel setting in TXDP Indirect Channel Control Register ###  set temp [expr 0x8000 | $channel]  admwr $devID 0xE701 $temp    # Poll BUSY bit until it is low  Poll_BUSY_Bit $devID 0xE701 15    ### 3. HDLC-Like Header or GFP Extended Header Configuration ###  # Note: The following example show how to configure the HDLC-like header for  #       LAPS encapsulation frame.  The same procedure can be used to setup   #       other HDLC-like encapsulation, and the same procedure can be used to   #       setup the optional EXI header for GFP encapsulation.    # first octet = HDR_CFRM_DAT [31:24] = Address (0x04)  # second octet = HDR_CFRM_DAT [23:16] = Control (0x03)  # third octet = HDR_CFRM_DAT [15:8] = 1st octet of SAPI (0xFE)  # forth octet = HDR_CFRM_DAT [7:0] = 2nd octet of SAPI (0x01)    if {$mode == 1} {      ### Setting HDLC-Like frame header for LAPS encapsulation    set hdr_cfrm_dat_31_24 0x04    set hdr_cfrm_dat_23_16 0x03    set hdr_cfrm_dat_15_8 0xFE    set hdr_cfrm_dat_7_0 0x01        # Write octets to data registers    admwr $devID 0xE709 [expr [expr $hdr_cfrm_dat_31_24 << 8]|$hdr_cfrm_dat_23_16]    admwr $devID 0xE708 [expr [expr $hdr_cfrm_dat_15_8 << 8]|$hdr_cfrm_dat_7_0]                # Activiating header setting in TXDP indirect extension header register     set burst_init 1 ;# set to 1 to indicate first set of writes    set burst_end0 1 ;# set to 1 to indicate hdr_cfrm_dat_7_0 is the last octet    set burst_end1 0    set burst_end2 0    set burst_end3 0            set value3 [expr [expr $burst_init << 8]|[expr $burst_end3 << 12]| \               [expr $burst_end2 << 11]|[expr $burst_end1 << 10]| \               [expr $burst_end0 << 9]|$channel]                   admwr $devID 0xE707 $value3        # Poll BUSY bit until it is low    Poll_BUSY_Bit $devID 0xE707 15  }    #########################################################################  #####                 Configuring RXDP Block                        #####  #########################################################################    ### 1. Enable RXDP Block ###  admwr $devID 0xE600 0x0001        #########################################################################    ### 2. Configuring GFP/HDLC-like Channel COnfiguation Ind. Reg. Group ###  ###    IREG_GRP[4:0] = 0x00                                           ###  #########################################################################      ### 2.1 Definding RXDP Channel Common Configuration Register Value ###      if {$mode == 0} {    # Recommended GFP Settings         set data_rev_obit 0    set data_rev_ibit 0    set pfcs_rev_fcsbyte 0    set pfcs_rev_fcsbit 0    set pfcs_rev_pldbit 0    set pfcs_inv 1    set pfcs_mode 1    set pfcs_chk $pfcs_ins      set descrmbl $scrmbl	    set encap_mode 0        set chan_en 1      } elseif {$mode == 1} {    # Recommened HDLC-Like Settings    set data_rev_obit 0    set data_rev_ibit 0    set pfcs_rev_fcsbyte 1    set pfcs_rev_fcsbit 1    set pfcs_rev_pldbit 1    set pfcs_inv 1        set pfcs_chk $pfcs_ins       set descrmbl $scrmbl                 set encap_mode 1        set chan_en 1  }      # Mapping bit to proper position    set data1 [expr 0x0040|[expr $data_rev_obit << 12]|[expr $data_rev_ibit << 11]| \             [expr $pfcs_rev_fcsbyte << 10]|[expr $pfcs_rev_fcsbit << 9]| \             [expr $pfcs_rev_pldbit << 8]|[expr $pfcs_inv << 7]| \             [expr $pfcs_mode << 5]|[expr $pfcs_chk << 4]|[expr $descrmbl << 3]| \             [expr $encap_mode << 2]|$chan_en]   ### 2.2 Definding RXDP Indirect Channel Specific Config Register Value ###  if {$mode == 0} {      # Set RESERVED_1 to 1 in GFP mode    set data2 0x0C7C  } elseif {$mode == 1} {        # Keep value in default in HDLC-Like mode    set data2 0x0000  }    ### 2.3 Write Data Content to Indirect Registers Group 0x00  ###  # a) Perform Indirect Read to Initialize Indirect Access  set req_busy 1  set rwb 1  set ireg_grp 0x0  set addr_value [expr [expr $req_busy << 15]|[expr $rwb << 14]| \                 [expr $ireg_grp << 5]|$channel]      admwr $devID 0xE601 $addr_value    Poll_BUSY_Bit $devID 0xE601 15 ;# Poll busy bit until low      # b) Write value Indirect Data Registers   admwr $devID 0xE602 $data1  admwr $devID 0xE603 $data2  admwr $devID 0xE604 0x0000  admwr $devID 0xE605 0xFFFF          # c) Activiate channel setting in RXDP Indirect Channel Control Register  set req_busy 1  set rwb 0  set ireg_grp 0x0  set addr_value [expr [expr $req_busy << 15]|[expr $rwb << 14]| \                 [expr $ireg_grp << 5]|$channel]        admwr $devID 0xE601 $addr_value        Poll_BUSY_Bit $devID 0xE601 15 ;# Poll busy bit until low    #########################################################################    ### 3. Configuring GFP Frame Filters in GFP/HDLC-like Channel         ###  ###    Configuation Ind. Reg. Group IREG_GRP[4:0] = 0x01 to 0x04      ###  ###    This section is applicable for GFP mode only                   ###  #########################################################################        if {$mode == 0} {        ### 3.1 Configure EXI Match and Extension Filter (Ind Reg Group 0x01) ###  # a) Perform Indirect Read to Initialize Indirect Access  set req_busy 1  set rwb 1  set ireg_grp 0x1  set addr_value [expr [expr $req_busy << 15]|[expr $rwb << 14]| \                 [expr $ireg_grp << 5]|$channel]      admwr $devID 0xE601 $addr_value    Poll_BUSY_Bit $devID 0xE601 15 ;# Poll busy bit until low      # b) Write value Indirect Data Registers   admwr $devID 0xE602 0x0  admwr $devID 0xE603 0x1  admwr $devID 0xE604 0x1  admwr $devID 0xE605 0x0          # c) Activiate channel setting in RXDP Indirect Channel Control Register  set req_busy 1  set rwb 0  set ireg_grp 0x1  set addr_value [expr [expr $req_busy << 15]|[expr $rwb << 14]| \                 [expr $ireg_grp << 5]|$channel]        admwr $devID 0xE601 $addr_value        Poll_BUSY_Bit $devID 0xE601 15 ;# Poll busy bit until low      ### 3.2a Configure Generic Filter Stage 0 (Ind Reg Group 0x02) ###     set req_busy 1  set rwb 1  set ireg_grp 0x2  set addr_value [expr [expr $req_busy << 15]|[expr $rwb << 14]| \                 [expr $ireg_grp << 5]|$channel]      admwr $devID 0xE601 $addr_value    Poll_BUSY_Bit $devID 0xE601 15 ;# Poll busy bit until low      # b) Write value Indirect Data Registers   admwr $devID 0xE602 0x0  admwr $devID 0xE603 0x0  admwr $devID 0xE604 0x0  admwr $devID 0xE605 0x0          # c) Activiate channel setting in RXDP Indirect Channel Control Register  set req_busy 1  set rwb 0  set ireg_grp 0x2  set addr_value [expr [expr $req_busy << 15]|[expr $rwb << 14]| \                 [expr $ireg_grp << 5]|$channel]        admwr $devID 0xE601 $addr_value        Poll_BUSY_Bit $devID 0xE601 15 ;# Poll busy bit until low    ### 3.2b Configure Generic Filter Stage 0 (Ind Reg Group 0x03) ###     set req_busy 1  set rwb 1  set ireg_grp 0x3  set addr_value [expr [expr $req_busy << 15]|[expr $rwb << 14]| \                 [expr $ireg_grp << 5]|$channel]      admwr $devID 0xE601 $addr_value    Poll_BUSY_Bit $devID 0xE601 15 ;# Poll busy bit until low      # b) Write value Indirect Data Registers   admwr $devID 0xE602 0x0  admwr $devID 0xE603 0x0  admwr $devID 0xE604 0x0  admwr $devID 0xE605 0x0          # c) Activiate channel setting in RXDP Indirect Channel Control Register  set req_busy 1  set rwb 0  set ireg_grp 0x3  set addr_value [expr [expr $req_busy << 15]|[expr $rwb << 14]| \                 [expr $ireg_grp << 5]|$channel]        admwr $devID 0xE601 $addr_value        Poll_BUSY_Bit $devID 0xE601 15 ;# Poll busy bit until low          ### 3.3 Configure Type Filter in GFP mode (Ind Reg Group 0x4) ###     # a) Perform Indirect Read to Initialize Indirect Access     set req_busy 1    set rwb 1    set ireg_grp 0x4    set addr_value [expr [expr $req_busy << 15]|[expr $rwb << 14]| \                   [expr $ireg_grp << 5]|$channel]        admwr $devID 0xE601 $addr_value      Poll_BUSY_Bit $devID 0xE601 15 ;# Poll busy bit until low        # b) Write value Indirect Data Registers     # Setting UPI0[7:0] to 0x00    # Setting PTI0[2:0] to 0x01 for Frame Mapped Ethernet                admwr $devID 0xE602 0x0100    admwr $devID 0xE603 0x0100    admwr $devID 0xE604 0x0100    admwr $devID 0xE605 0x0100            # c) Activiate channel setting in TXDP Indirect Channel Control Register    set req_busy 1    set rwb 0    set ireg_grp 0x4    set addr_value [expr [expr $req_busy << 15]|[expr $rwb << 14]| \                   [expr $ireg_grp << 5]|$channel]          admwr $devID 0xE601 $addr_value          Poll_BUSY_Bit $devID 0xE601 15 ;# Poll busy bit until low       }      #########################################################################    ### 4. Configuring HDLC-Like Frame Filters in GFP/HDLC-like Channel   ###  ###    Configuation Ind. Reg. Group IREG_GRP[4:0] = 0x01 to 0x04.     ###  ###    This section is applicable for HDLC-Like frame mode only       ###  #########################################################################   if {$mode == 1} {           ### 4.1 Configure Generic Filter Stage 0 (Ind Reg Group 0x02 and 0x03) ###    # TBD          ### 4.2 Configure Generic Filter Stage 1 (Ind Reg Group 0x4) ###     # TBD      }}#------------------------------------------------------------------------------# SCRIPT NAME:	EOS_Payload_Config## DESCRIPTION:	This procedure setup the payload configuration in the EOS#               Subsystem.#		# PARAMETERS:   devID - This parameter is used to specify the device #                       under configuration#		payload	- STS-1, STS-3c, STS-12c, VT15, #                         AU3/C3, AU4/C4, AU4-4c, AU3/TU12, AU4/TU12, AU4/TU3#             # NOTES:        This procedure setups the complete STS-12/STM-4 data stream#               to carry the same payload type in both add and drop direction.#               This procedure needs to be modify for mixing payload.## REVISION History:# Preliminary 1 - Script created# Released 2 - Corrected SIRP settings for AU4 (STS-3c) and AU4-4c (STS-12c) modes##------------------------------------------------------------------------------proc EOS_Payload_Config {devID payload} {  source /usr/lib/cgi-bin/apps/tclscripts/PM5337_util.tcl      ###########################################################################  #####           Setting High Order Payload Configuration              #####  ###########################################################################    # Setting EOS Subsystem Level Drop and Add SONET/SDH Payload   # Configuration Register (0xE030 - drop config , 0xE031 - add config)    if {$payload == "STS-1" || $payload == "AU3/C3"} {    ### Configuration for STS-1 with no VT or AU3/C3 ###    set activeTU 0x0	;# no VT/TU            # Subsystem level configuration    admwr $devID 0xE030 0x2FFF0000    admwr $devID 0xE031 0x0FFF0000        # TVCP payload configuration    admwr $devID 0xE501 0xFFFF  ;# STS3_1    admwr $devID 0xE502 0xFFFF	;# STS3_2    admwr $devID 0xE503 0xFFFF	;# STS3_3    admwr $devID 0xE504 0xFFF0	;# TUG3    admwr $devID 0xE505 0x0FFF	;# HO_SEL               # RVCP payload configuration    admwr $devID 0xE401 0xFFFF	;# STS3_1    admwr $devID 0xE402 0xFFFF	;# STS3_2    admwr $devID 0xE403 0xFFFF	;# STS3_3    admwr $devID 0xE404 0xFFF0	;# TUG3    admwr $devID 0xE405 0x0FFF	;# HO_SEL            # [AL] Added Jan 05, 2006    #####################    ### SIRP Settings ###    #####################          # SIRP Settings        admwrb $devID 0xE340 0 1     admwrb $devID 0xE341 0 1    admwrb $devID 0xE342 0 1    admwrb $devID 0xE343 0 1    admwrb $devID 0xE344 0 1    admwrb $devID 0xE345 0 1