/*
 *  Copyright 2003 by Texas Instruments Incorporated.
 *  All rights reserved. Property of Texas Instruments Incorporated.
 *  Restricted rights to use, duplicate or disclose this code are
 *  granted through contract.
 *  
 */
/* "@(#) DDK 1.11.00.00 11-04-03 (ddk-b13)" */
/* 
 *  ======== dsk5416_dma_pcm3002.c ========
 * 
 *  DMA interrupt-driven low-level streaming device driver for TI
 *  5416 DSK. Uses the C54x Chip Support Library. 
 *
 *  DSP/BIOS configuration:
 *     DMA channel 4 RX ISR plugged to DSK5416_DMA_PCM3002_isr with arg = 0
 *     DMA channel 5 TX ISR plugged to DSK5416_DMA_PCM3002_isr with arg = 1
 */

#include <std.h>

#include <csl.h>
#include <csl_dma.h>
#include <csl_mcbsp.h>

#include <iom.h>

#include <c54xx_dma_mcbsp.h>
#include <dsk5416_dma_pcm3002.h>
#include <dsk5416_pcm3002.h>
#include <dsk5416.h>

/*
 * Forward declaration of IOM interface functions.
 */
static Int mdBindDev(Ptr *devp, Int devid, Ptr devParams);
static Int mdCreateChan(Ptr *chanp, Ptr devp, String name, Int mode,
        Ptr chanParams, IOM_TiomCallback cbFxn, Ptr cbArg);

/*
 * Public IOM interface table.
 */
IOM_Fxns DSK5416_DMA_PCM3002_FXNS;

/* CSL config structure for McBSP */
static MCBSP_Config mcbspCfg = {
    0x2000,        /*  Serial Port Control Register 1   */
    0x0200,        /*  Serial Port Control Register 2   */
    0x0340,        /*  Receive Control Register 1   */
    0x0340,        /*  Receive Control Register 2   */
    0x0340,        /*  Transmit Control Register 1   */
    0x0340,        /*  Transmit Control Register 2   */
    0x1f00,        /*  Sample Rate Generator Register 1   */
    0x003f,        /*  Sample Rate Generator Register 2   */
    0x0001,        /*  Multichannel Control Register 1   */
    0x0001,        /*  Multichannel Control Register 2   */
    0x0083,        /*  Pin Control Register   */
    0x0005,        /*  Receive Channel Enable Register Partition A   */
    0x0000,        /*  Receive Channel Enable Register Partition B   */
    0x0000,        /*  Receive Channel Enable Register Partition C   */ 
    0x0000,        /*  Receive Channel Enable Register Partition D   */ 
    0x0000,        /*  Receive Channel Enable Register Partition E   */
    0x0000,        /*  Receive Channel Enable Register Partition F   */
    0x0000,        /*  Receive Channel Enable Register Partition G   */  
    0x0000,        /*  Receive Channel Enable Register Partition H   */
    0x000a,        /*  Transmit Channel Enable Register Partition A   */  
    0x0000,        /*  Transmit Channel Enable Register Partition B   */
    0x0000,        /*  Transmit Channel Enable Register Partition C   */ 
    0x0000,        /*  Transmit Channel Enable Register Partition D   */ 
    0x0000,        /*  Transmit Channel Enable Register Partition E   */
    0x0000,        /*  Transmit Channel Enable Register Partition F   */ 
    0x0000,        /*  Transmit Channel Enable Register Partition G   */ 
    0x0000         /*  Transmit Channel Enable Register Partition H   */
};

/*  CSL config structure for DMAs */
static DMA_Config dmaRxCfg = {
    0x0000,     /*  Channel Priority (0x0000 or 0x0001)  */
    0x0000,     /*  Global Reload Register Usage */
    0x4045,     /*  Transfer Mode Control Register (DMMCR)  */
    0x3000,     /*  Sync Event and Frame Count Register (DMSFC)  */
    (DMA_AdrPtr)0x0031, /*  Source Address Register (DMSRC) - Numeric  */
    (DMA_AdrPtr)0x0000, /*  Destination Address Register (DMDST) - Numeric  */
    0x0000,     /*  Element Count Register (DMCTR)  */
    (DMA_AdrPtr)0x0000, /*  Global Source Address Reload Register (DMGSA) */
    (DMA_AdrPtr)0x0000, /*  Global Destination Address Reload Reg (DMGDA)*/
    0x0000,     /*  Global Element Count Reload Register (DMGCR)  */
    0x0000      /*  Global Frame Count Reload Register (DMGFR)  */
};

static DMA_Config dmaTxCfg = {
    0x0000,     /*  Channel Priority (0x0000 or 0x0001)  */
    0x0000,     /*  Global Reload Register Usage */
    0x4141,     /*  Transfer Mode Control Register (DMMCR)  */
    0x4000,     /*  Sync Event and Frame Count Register (DMSFC)  */
    (DMA_AdrPtr)0x0000, /*  Source Address Register (DMSRC) - Numeric  */
    (DMA_AdrPtr)0x0033, /*  Destination Address Register (DMDST) */
    0x0000,     /*  Element Count Register (DMCTR)  */
    (DMA_AdrPtr)0x0000, /*  Global Source Address Reload Register (DMGSA) */
    (DMA_AdrPtr)0x0000, /*  Global Destination Address Reload Reg (DMGDA) */
    0x0000,     /*  Global Element Count Reload Register (DMGCR)  */
    0x0000      /*  Global Frame Count Reload Register (DMGFR)  */
};

/* declare global MCBSP handle for use with BSL */ 
MCBSP_Handle        C54XX_DMA_MCBSP_hMcbsp;

/*
 *  ======== mdBindDev ========
 */
#pragma CODE_SECTION(mdBindDev, ".text:init")
static Int mdBindDev(Ptr *devp, Int devid, Ptr devParams)
{
    DSK5416_DMA_PCM3002_DevParams *params =
        (DSK5416_DMA_PCM3002_DevParams *)devParams;
    C54XX_DMA_MCBSP_DevParams genericDevParams;
    DSK5416_PCM3002_CodecHandle codec;
    DSK5416_DMA_PCM3002_DevParams defaultParams = 
                        DSK5416_DMA_PCM3002_DEVPARAMS_DEFAULT;

    /* use default parameters if none are given */
    if (params == NULL) {
        params = &defaultParams;
    }

    /* Check the version number */
    if (params->versionId != DSK5416_DMA_PCM3002_VERSION_1){
        /* Unsupported version */
        return(IOM_EBADARGS);
    }

    /* open and configure the McBSP to call BSL open and close the codec */
    C54XX_DMA_MCBSP_hMcbsp = MCBSP_open(MCBSP_PORT2, MCBSP_OPEN_RESET);

    if (C54XX_DMA_MCBSP_hMcbsp == INV) {
        return (IOM_EBADIO);
    }

    MCBSP_config(C54XX_DMA_MCBSP_hMcbsp, &mcbspCfg);

    /* set codec parameters (this will also initialize the codec) */
    codec = DSK5416_PCM3002_openCodec(0, &(params->pcm3002));

    /* this closes the mcbsp */
    DSK5416_PCM3002_closeCodec(codec);
    
    genericDevParams.versionId = C54XX_DMA_MCBSP_VERSION_1;
    genericDevParams.rxDmaId = params->rxDmaId;
    genericDevParams.txDmaId = params->txDmaId;
    genericDevParams.mcbspCfg = &mcbspCfg;
    genericDevParams.rxIntrMask = params->rxIntrMask;
    genericDevParams.txIntrMask = params->txIntrMask;

    return (C54XX_DMA_MCBSP_FXNS.mdBindDev(devp, MCBSP_PORT2,
            &genericDevParams));
}

/*
 *  ======== mdCreateChan ========
 */
static Int mdCreateChan(Ptr *chanp, Ptr devp, String name, Int mode,
                Ptr chanParams, IOM_TiomCallback cbFxn, Ptr cbArg)
{
    C54XX_DMA_MCBSP_ChanParams genericChanParams;

    if (mode == IOM_INPUT) {
        genericChanParams.dmaCfg = &dmaRxCfg;
    }
    else if (mode == IOM_OUTPUT) {
        genericChanParams.dmaCfg = &dmaTxCfg;
    }
    else {
        return (IOM_EBADMODE);
    }

    return (C54XX_DMA_MCBSP_FXNS.mdCreateChan(chanp, devp, name, mode,
        &genericChanParams, cbFxn, cbArg));
}

/*
 *  ======== DSK5416_DMA_PCM3002_init ========
 *
 *  Controller initialization function
 */
#pragma CODE_SECTION(DSK5416_DMA_PCM3002_init, ".text:init")
Void DSK5416_DMA_PCM3002_init(Void)
{
    /* initialize the board */
    DSK5416_init();

    /*
     * Use C54XX_DMA_MCBSP_FXNS functions for the heart of the 
     * controller.  This is common DMA/MCBSP code that works for
     * many DMA/MCBSP/codec combinations.
     */
    C54XX_DMA_MCBSP_init();

    DSK5416_DMA_PCM3002_FXNS = C54XX_DMA_MCBSP_FXNS;
    DSK5416_DMA_PCM3002_FXNS.mdBindDev = mdBindDev;
    DSK5416_DMA_PCM3002_FXNS.mdCreateChan = mdCreateChan;
}