?? dsk5510_dma_aic23.c
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/*
* Copyright 2003 by Texas Instruments Incorporated.
* All rights reserved. Property of Texas Instruments Incorporated.
* Restricted rights to use, duplicate or disclose this code are
* granted through contract.
*
*/
/* "@(#) DDK 1.11.00.00 11-04-03 (ddk-b13)" */
/*
* ======== dsk5510_dma_aic23.c ========
*
* DMA interrupt-driven low-level streaming device driver for TI
* 5510 DSK. Uses the C55x Chip Support Library.
*
* DSP/BIOS configuration:
* DMA channel 4 RX ISR plugged to DSK5510_DMA_AIC23_isr with arg = 0
* DMA channel 5 TX ISR plugged to DSK5510_DMA_AIC23_isr with arg = 1
*/
#include <std.h>
#include <csl.h>
#include <csl_dma.h>
#include <csl_mcbsp.h>
#include <iom.h>
#include <c55xx_dma_mcbsp.h>
#include <dsk5510_dma_aic23.h>
#include <aic23.h>
/*
* Forward declaration of IOM interface functions.
*/
static Int mdBindDev(Ptr *hDevice, Int devid, Ptr devParams);
static Int mdCreateChan(Ptr *chanp, Ptr devp, String name, Int mode,
Ptr chanParams, IOM_TiomCallback cbFxn, Ptr cbArg);
/*
* Public IOM interface table.
*/
IOM_Fxns DSK5510_DMA_AIC23_FXNS;
/* CSL handle to the McBSP2. The McBSP is shared between the two channels */
static MCBSP_Config mcbspCfg2 = {
MCBSP_SPCR1_RMK(
MCBSP_SPCR1_DLB_OFF, /* DLB = 0 */
MCBSP_SPCR1_RJUST_RZF, /* RJUST = 0 */
MCBSP_SPCR1_CLKSTP_DISABLE, /* CLKSTP = 0 */
MCBSP_SPCR1_DXENA_NA, /* DXENA = 0 */
MCBSP_SPCR1_ABIS_DISABLE, /* ABIS = 0 */
MCBSP_SPCR1_RINTM_RRDY, /* RINTM = 0 */
0, /* RSYNCER = 0 */
0, /* RFULL = 0 */
0, /* RRDY = 0 */
MCBSP_SPCR1_RRST_DISABLE /* RRST = 0 */
),
MCBSP_SPCR2_RMK(
MCBSP_SPCR2_FREE_NO, /* FREE = 0 */
MCBSP_SPCR2_SOFT_YES, /* SOFT = 1 */
MCBSP_SPCR2_FRST_RESET, /* FRST = 0 */
MCBSP_SPCR2_GRST_RESET, /* GRST = 0 */
MCBSP_SPCR2_XINTM_XRDY, /* XINTM = 0 */
0, /* XSYNCER = 0 */
0, /* XEMPTY = 0 */
0, /* XRDY = 0 */
MCBSP_SPCR2_XRST_DISABLE /* XRST = 0 */
),
MCBSP_RCR1_RMK(
MCBSP_RCR1_RFRLEN1_OF(1), /* RFRLEN1 = 1 */
MCBSP_RCR1_RWDLEN1_16BIT /* RWDLEN1 = 2 */
),
MCBSP_RCR2_RMK(
MCBSP_RCR2_RPHASE_SINGLE, /* RPHASE = 0 */
MCBSP_RCR2_RFRLEN2_OF(0), /* RFRLEN2 = 0 */
MCBSP_RCR2_RWDLEN2_8BIT, /* RWDLEN2 = 0 */
MCBSP_RCR2_RCOMPAND_MSB, /* RCOMPAND = 0 */
MCBSP_RCR2_RFIG_YES, /* RFIG = 0 */
MCBSP_RCR2_RDATDLY_0BIT /* RDATDLY = 0 */
),
MCBSP_XCR1_RMK(
MCBSP_XCR1_XFRLEN1_OF(1), /* XFRLEN1 = 1 */
MCBSP_XCR1_XWDLEN1_16BIT /* XWDLEN1 = 2 */
),
MCBSP_XCR2_RMK(
MCBSP_XCR2_XPHASE_SINGLE, /* XPHASE = 0 */
MCBSP_XCR2_XFRLEN2_OF(0), /* XFRLEN2 = 0 */
MCBSP_XCR2_XWDLEN2_8BIT, /* XWDLEN2 = 0 */
MCBSP_XCR2_XCOMPAND_MSB, /* XCOMPAND = 0 */
MCBSP_XCR2_XFIG_YES, /* XFIG = 0 */
MCBSP_XCR2_XDATDLY_0BIT /* XDATDLY = 0 */
),
MCBSP_SRGR1_RMK(
MCBSP_SRGR1_FWID_OF(0), /* FWID = 0 */
MCBSP_SRGR1_CLKGDV_OF(0) /* CLKGDV = 0 */
),
MCBSP_SRGR2_RMK(
MCBSP_SRGR2_GSYNC_FREE, /* FREE = 0 */
MCBSP_SRGR2_CLKSP_RISING, /* CLKSP = 0 */
MCBSP_SRGR2_CLKSM_CLKS, /* CLKSM = 0 */
MCBSP_SRGR2_FSGM_DXR2XSR, /* FSGM = 0 */
MCBSP_SRGR2_FPER_OF(0) /* FPER = 0 */
),
MCBSP_MCR1_DEFAULT,
MCBSP_MCR2_DEFAULT,
MCBSP_PCR_RMK(
MCBSP_PCR_IDLEEN_RESET, /* IDLEEN = 0 */
MCBSP_PCR_XIOEN_SP, /* XIOEN = 0 */
MCBSP_PCR_RIOEN_SP, /* RIOEN = 0 */
MCBSP_PCR_FSXM_EXTERNAL, /* FSXM = 0 */
MCBSP_PCR_FSRM_EXTERNAL, /* FSRM = 0 */
MCBSP_PCR_SCLKME_NO, /* SCLKME = 0 */
0, /* CLKSSTAT = 0 */
0, /* DXSTAT = 0 */
0, /* DRSTAT = 0 */
MCBSP_PCR_CLKXM_INPUT, /* CLKXM = 0 */
MCBSP_PCR_CLKRM_INPUT, /* CLKRM = 0 */
MCBSP_PCR_FSXP_ACTIVEHIGH, /* FSXP = 0 */
MCBSP_PCR_FSRP_ACTIVEHIGH, /* FSRP = 0 */
MCBSP_PCR_CLKXP_FALLING, /* CLKXP = 1 */
MCBSP_PCR_CLKRP_RISING /* CLKRP = 1 */
),
MCBSP_RCERA_DEFAULT,
MCBSP_RCERB_DEFAULT,
MCBSP_RCERC_DEFAULT,
MCBSP_RCERD_DEFAULT,
MCBSP_RCERE_DEFAULT,
MCBSP_RCERF_DEFAULT,
MCBSP_RCERG_DEFAULT,
MCBSP_RCERH_DEFAULT,
MCBSP_XCERA_DEFAULT,
MCBSP_XCERB_DEFAULT,
MCBSP_XCERC_DEFAULT,
MCBSP_XCERD_DEFAULT,
MCBSP_XCERE_DEFAULT,
MCBSP_XCERF_DEFAULT,
MCBSP_XCERG_DEFAULT,
MCBSP_XCERH_DEFAULT
};
/* CSL to handle the DMA Channels 4 and 5 */
static DMA_Config dmaRxCfg = {
0, /* DMACSDP will be initialized by mdBindDev */
DMA_DMACCR_RMK(
DMA_DMACCR_DSTAMODE_POSTINC,
DMA_DMACCR_SRCAMODE_CONST,
DMA_DMACCR_ENDPROG_OFF,
DMA_DMACCR_REPEAT_OFF,
DMA_DMACCR_AUTOINIT_OFF,
DMA_DMACCR_EN_STOP,
DMA_DMACCR_PRIO_HI,
DMA_DMACCR_FS_DISABLE,
DMA_DMACCR_SYNC_REVT2
), /* DMACCR */
DMA_DMACICR_RMK(
DMA_DMACICR_BLOCKIE_OFF,
DMA_DMACICR_LASTIE_OFF,
DMA_DMACICR_FRAMEIE_ON,
DMA_DMACICR_FIRSTHALFIE_OFF,
DMA_DMACICR_DROPIE_OFF,
DMA_DMACICR_TIMEOUTIE_OFF
), /* DMACICR */
(DMA_AdrPtr)((Uint32)(_MCBSP_DRR12_ADDR<<1)), /*DMACSSAL=MCBSP2 DRR*/
0x0000, /* DMACSSAU */
(DMA_AdrPtr)0x0000, /* DMACDSAL, to be loaded by submit */
0x0000, /* DMACDSAU */
0x0000, /* DMACEN */
0x0001, /* DMACFN */
0x0000, /* DMACFI */
0x0000 /* DMACEI */
};
static DMA_Config dmaTxCfg = {
0, /* DMACSDP will be initialized by mdBindDev */
DMA_DMACCR_RMK(
DMA_DMACCR_DSTAMODE_CONST,
DMA_DMACCR_SRCAMODE_POSTINC,
DMA_DMACCR_ENDPROG_OFF,
DMA_DMACCR_REPEAT_OFF,
DMA_DMACCR_AUTOINIT_OFF,
DMA_DMACCR_EN_STOP,
DMA_DMACCR_PRIO_HI,
DMA_DMACCR_FS_DISABLE,
DMA_DMACCR_SYNC_XEVT2
), /* DMACCR */
DMA_DMACICR_RMK(
DMA_DMACICR_BLOCKIE_OFF,
DMA_DMACICR_LASTIE_OFF,
DMA_DMACICR_FRAMEIE_ON,
DMA_DMACICR_FIRSTHALFIE_OFF,
DMA_DMACICR_DROPIE_OFF,
DMA_DMACICR_TIMEOUTIE_OFF
), /* DMACICR */
(DMA_AdrPtr)0x0000, /* DMACSSAL, to be loaded by submit */
0x0000, /* DMACSSAU */
(DMA_AdrPtr)((Uint32)(_MCBSP_DXR12_ADDR<<1)), /* DMACDSAL=MCBSP2 DXR */
0x0000, /* DMACDSAU */
0x0000, /* DMACEN */
0x0001, /* DMACFN */
0x0000, /* DMACFI */
0x0000 /* DMACEI */
};
/*
* These arrays are used to initialized csdp value for different DMA port
* type. This is done by mdBindDev using params->dmaPortType
*/
static Uns rxCsdpValue[3] = {
DMA_DMACSDP_RMK( /* DSK5510_DMA_AIC23_PORTTYPE_DARAM */
DMA_DMACSDP_DSTBEN_NOBURST,
DMA_DMACSDP_DSTPACK_OFF,
DMA_DMACSDP_DST_DARAM,
DMA_DMACSDP_SRCBEN_NOBURST,
DMA_DMACSDP_SRCPACK_OFF,
DMA_DMACSDP_SRC_PERIPH,
DMA_DMACSDP_DATATYPE_16BIT
),
DMA_DMACSDP_RMK( /* DSK5510_DMA_AIC23_PORTTYPE_SARAM */
DMA_DMACSDP_DSTBEN_NOBURST,
DMA_DMACSDP_DSTPACK_OFF,
DMA_DMACSDP_DST_SARAM,
DMA_DMACSDP_SRCBEN_NOBURST,
DMA_DMACSDP_SRCPACK_OFF,
DMA_DMACSDP_SRC_PERIPH,
DMA_DMACSDP_DATATYPE_16BIT
),
DMA_DMACSDP_RMK( /* DSK5510_DMA_AIC23_PORTTYPE_EMIF */
DMA_DMACSDP_DSTBEN_NOBURST,
DMA_DMACSDP_DSTPACK_OFF,
DMA_DMACSDP_DST_EMIF,
DMA_DMACSDP_SRCBEN_NOBURST,
DMA_DMACSDP_SRCPACK_OFF,
DMA_DMACSDP_SRC_PERIPH,
DMA_DMACSDP_DATATYPE_16BIT
)
};
static Uns txCsdpValue[3] = {
DMA_DMACSDP_RMK( /* DSK5510_DMA_AIC23_PORTTYPE_DARAM */
DMA_DMACSDP_DSTBEN_NOBURST,
DMA_DMACSDP_DSTPACK_OFF,
DMA_DMACSDP_DST_PERIPH,
DMA_DMACSDP_SRCBEN_NOBURST,
DMA_DMACSDP_SRCPACK_OFF,
DMA_DMACSDP_SRC_DARAM,
DMA_DMACSDP_DATATYPE_16BIT
),
DMA_DMACSDP_RMK( /* DSK5510_DMA_AIC23_PORTTYPE_SARAM */
DMA_DMACSDP_DSTBEN_NOBURST,
DMA_DMACSDP_DSTPACK_OFF,
DMA_DMACSDP_DST_PERIPH,
DMA_DMACSDP_SRCBEN_NOBURST,
DMA_DMACSDP_SRCPACK_OFF,
DMA_DMACSDP_SRC_SARAM,
DMA_DMACSDP_DATATYPE_16BIT
),
DMA_DMACSDP_RMK( /* DSK5510_DMA_AIC23_PORTTYPE_EMIF */
DMA_DMACSDP_DSTBEN_NOBURST,
DMA_DMACSDP_DSTPACK_OFF,
DMA_DMACSDP_DST_PERIPH,
DMA_DMACSDP_SRCBEN_NOBURST,
DMA_DMACSDP_SRCPACK_OFF,
DMA_DMACSDP_SRC_EMIF,
DMA_DMACSDP_DATATYPE_16BIT
)
};
/*
* ======== mdBindDev ========
*/
#pragma CODE_SECTION(mdBindDev, ".text:init")
static Int mdBindDev(Ptr *devp, Int devid, Ptr devParams)
{
DSK5510_DMA_AIC23_DevParams *params =
(DSK5510_DMA_AIC23_DevParams *)devParams;
C55XX_DMA_MCBSP_DevParams genericDevParams;
DSK5510_DMA_AIC23_DevParams defaultParams =
DSK5510_DMA_AIC23_DEVPARAMS_DEFAULT;
/* use default parameters if none are given */
if (params == NULL) {
params = &defaultParams;
}
/* Check the version number */
if (params->versionId != DSK5510_DMA_AIC23_VERSION_1){
/* Unsupported version */
return(IOM_EBADARGS);
}
/* set codec parameters (this will also initialize the codec) */
if (!AIC23_setParams(&(params->aic23))) {
return(IOM_EBADIO);
}
/* set dmacsdp register to the right dma port type */
dmaRxCfg.dmacsdp = rxCsdpValue[params->dmaPortType];
dmaTxCfg.dmacsdp = txCsdpValue[params->dmaPortType];
genericDevParams.versionId = C55XX_DMA_MCBSP_VERSION_1;
genericDevParams.rxDmaId = params->rxDmaId;
genericDevParams.txDmaId = params->txDmaId;
genericDevParams.mcbspCfg = &mcbspCfg2;
genericDevParams.rxIerMask[0] = params->rxIerMask[0];
genericDevParams.rxIerMask[1] = params->rxIerMask[1];
genericDevParams.txIerMask[0] = params->txIerMask[0];
genericDevParams.txIerMask[1] = params->txIerMask[1];
return (C55XX_DMA_MCBSP_FXNS.mdBindDev(devp, MCBSP_PORT2,
&genericDevParams));
}
/*
* ======== mdCreateChan ========
*/
static Int mdCreateChan(Ptr *chanp, Ptr devp, String name, Int mode,
Ptr chanParams, IOM_TiomCallback cbFxn, Ptr cbArg)
{
C55XX_DMA_MCBSP_ChanParams genericChanParams;
if (mode == IOM_INPUT) {
genericChanParams.dmaCfg = &dmaRxCfg;
}
else if (mode == IOM_OUTPUT) {
genericChanParams.dmaCfg = &dmaTxCfg;
}
else {
return (IOM_EBADMODE);
}
return (C55XX_DMA_MCBSP_FXNS.mdCreateChan(chanp, devp, name, mode,
&genericChanParams, cbFxn, cbArg));
}
/*
* ======== DSK5510_DMA_AIC23_init ========
*
* Controller initialization function
*/
#pragma CODE_SECTION(DSK5510_DMA_AIC23_init, ".text:init")
Void DSK5510_DMA_AIC23_init(Void)
{
/*
* Use C55XX_DMA_MCBSP_FXNS functions for the heart of the
* controller. This is common DMA/MCBSP code that works for
* many DMA/MCBSP/codec combinations.
*/
C55XX_DMA_MCBSP_init();
DSK5510_DMA_AIC23_FXNS = C55XX_DMA_MCBSP_FXNS;
DSK5510_DMA_AIC23_FXNS.mdBindDev = mdBindDev;
DSK5510_DMA_AIC23_FXNS.mdCreateChan = mdCreateChan;
}
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