?? startup.s
字號:
;; ---------------------------- 0x0c7FFFFF
;; | Interrupt Handler |
;; |----------------------------|0x0C7FFF00
;; | STACK AREA |
;; |----------------------------|0x0C700000
;; | HEAP AREA(R/W base) |
;; |----------------------------|0x0C100000 DATA AREA(R/W AND ZI)
;; | APPLICATION AREA(SDRAM) |
;; |----------------------------|0x0C000000 SDRAM APPLICATION RO BASE of HY57V641620HG(1M X 16bit X 4bank)
;; | RESERVED |
;; |----------------------------|0x08000000
;; | RESERVED |
;; |----------------------------|0x06000000
;; | nGCS2 |
;; |----------------------------|0x04000000
;; | RESERVED |
;; |----------------------------|0x02000000
;; | SFR |
;; |----------------------------|0x01C00000
;; | RESERVED |
;; |----------------------------|0x00020000 (128KBYTE)
;; | BOOT ROM (39VF160) |
;; ---------------------------- 0x00000000 BOOT RO BASE 0x00
_ISR_STARTADDRESS EQU 0x0c7fff00 ;GCS6(nSCS0):8MByte SDRAM
;Pre-defined constants
USERMODE EQU 0x10
FIQMODE EQU 0x11
IRQMODE EQU 0x12
SVCMODE EQU 0x13
ABORTMODE EQU 0x17
UNDEFMODE EQU 0x1b
MODEMASK EQU 0x1f
NOINT EQU 0xc0
AREA Init,CODE,READONLY
GET 44b0.s
IMPORT |Image$$BOOTROM$$Limit|
IMPORT |Image$$SDRAM$$Base|
IMPORT |Image$$SDRAM$$Limit|
IMPORT |Image$$SDRAM$$Length|
IMPORT |Image$$SDRAM1$$ZI$$Base|
IMPORT |Image$$SDRAM1$$ZI$$Limit|
IMPORT |Image$$SDRAM1$$Base|
IMPORT |Image$$SDRAM1$$Limit|
IMPORT |Image$$SDRAM1$$Length|
IMPORT Main
ENTRY
b ResetHandler ;for debug 0x00
b HandlerUndef ;handlerUndef 0x04
b HandlerSWI ;SWI interrupt handler 0x08
b HandlerPabort ;handlerPAbort 0x0c
b HandlerDabort ;handlerDAbort 0x10
b . ;handlerReserved 0x14
b HandlerIRQ ;0x18
b HandlerFIQ ;0x1c
;***************
;* START *
;***************
ResetHandler
ldr r0,=WTCON ;watch dog disable
ldr r1,=0x0
str r1,[r0]
ldr r0,=1000
delay1
sub r0,r0,#1
cmp r0,#0x1
bne delay1
ldr r0,=SYSCFG ;enable writer buffer, full cache enable, stall disable
ldr r1,=0x0
str r1,[r0]
ldr r0,=NCACHBE0 ;non cacheable area control
ldr r1,=0x80002000 ;bank1,2,3 area
str r1,[r0]
ldr r0,=INTMSK
ldr r1,=0x07ffffff ;all interrupt disable
str r1,[r0]
;****************************************************
;* Configuration Port control registers *
;****************************************************
;PA9--PA0
;OUT OUT ADDR22 ADDR21 ADDR20 ADDR19 ADDR18 ADDR17 ADDR16 ADDR0
; 0 0 1 1 1 1 1 1 1 1
ldr r1,=PCONA
ldr r0,=0xff
str r0,[r1]
;PB10--PB0
;nGCS5 nGCS4 OUT OUT OUT nWBE3 nWBE2 nSRAS nSCAS SCLK SCKE
; 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1
ldr r1,=PCONB
ldr r0,=0x63f
str r0,[r1]
;PC15--PC0
;nCTS0 nRTS0 RXD1 TXD1 nCTS1 nRTS1 OUT OUT VD4 VD5 V6D VD7 OUT OUT OUT OUT
; 11 11 11 11 11 11 01 01 11 11 11 11 01 01 01 01
ldr r1,=PCONC
ldr r0,=0xfff5ff55
str r0,[r1]
ldr r1,=PUPC
ldr r0,=0xffff ;DISABLE PULL-UP
str r0,[r1]
ldr r1,=PDATC
ldr r0,=0x0
str r0,[r1]
;PD7-PD0
;VFRAME VM VLINE VCLK VD3 VD2 VD1 VD0
; 10 10 10 10 10 10 10 10
ldr r1,=PCOND
ldr r0,=0xaaaa
str r0,[r1]
ldr r1,=PUPD
ldr r0,=0xff ;DISABLE PULL-UP
str r0,[r1]
;PE8--PE0
;ENDIAN OUT OUT OUT OUT OUT RXD0 TXD0 OUT
; 00 01 01 01 01 01 10 10 01
ldr r1,=PCONE
ldr r0,=0x5569
str r0,[r1]
ldr r1,=PUPE
ldr r0,=0xff ;DISABLE PULL-UP
str r0,[r1]
;PF8-PF0
;IISCLK IISDI IISDO IISLRCK OUT OUT OUT IICSDA IICSCL
; 100 100 100 100 01 01 01 10 10
ldr r1,=PCONF
ldr r0,=0x24915a
str r0,[r1]
ldr r1,=PUPF
ldr r0,=0x0 ;ENABLE PULL-UP
str r0,[r1]
;PG7--PG0
;INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
; 11 11 11 11 11 11 11 11
ldr r1,=PCONG
ldr r0,=0xffff
str r0,[r1]
ldr r1,=PUPG
ldr r0,=0x00 ;ENABLE PULL-UP
str r0,[r1]
; Clock configration
ldr r0,=LOCKTIME ;PLL lock counter value
ldr r1,=800
str r1,[r0]
ldr r0,=PLLCON ;Fout=(MDIV+8)*Fin/((PDIV+2)*2^SDIV)
;Fout*2^SDIV<170 and 1<Fin/(PDIV+2)<2
;MDIV=bit 19-12,PDIV=bit 9-4 SDIV=bit 1-0
ldr r1,=0x60 ;1倍頻
;ldr r1,=0x10021 ;3倍頻
str r1,[r0]
ldr r0,=CLKCON ;enable peripherals clock
ldr r1,=0x7ff8
str r1,[r0]
;Memory configration
ldr r0,=SMRDATA
ldmia r0,{r1-r13}
ldr r0,=BWSCON
stmia r0,{r1-r13}
;****************************************************
;* Initialize stacks *
;****************************************************
ldr sp, =SVCStack
bl InitStacks
;Initialize I/O output value
ldr r0,=|Image$$BOOTROM$$Limit|
ldr r1,=|Image$$SDRAM$$Limit|
ldr r3,=|Image$$SDRAM$$Length|
ldr r4,=|Image$$SDRAM$$Base|
ldr r5,=0
0
cmp r5, r3 ; Copy prog to SDRAM
ldrcc r2, [r0],#4 ;--> LDRCC r2, [r0] + ADD r0, r0, #4
strcc r2, [r4],#4 ;--> STRCC r2, [r1] + ADD r1, r1, #4
add r5,r5,#4
bcc %b0
ldr r3,=|Image$$SDRAM1$$Base|
ldr r1,=|Image$$SDRAM1$$Length|
ldr r5,=0
1
cmp r5, r1 ; Copy init data
ldrcc r2, [r0],#4 ;--> LDRCC r2, [r0] + ADD r0, r0, #4
strcc r2, [r3],#4 ;--> STRCC r2, [r1] + ADD r1, r1, #4
add r5,r5,#4
bcc %b1
;Zero init base => top of initialised data
ldr r3, =|Image$$SDRAM1$$ZI$$Base|
; Top of zero init segment
ldr r1, =|Image$$SDRAM1$$ZI$$Limit|
mov r2, #0
2
cmp r3, r1 ; Zero init
strcc r2, [r3],#4
bcc %b2
;init interrupt controller
ldr r0,=INTMOD ;all interrupt is IRQ interrupt
ldr r1,=0x0
str r1,[r0]
ldr r0,=EXTINT
ldr r1,=0x0
str r1,[r0]
ldr r0,=INTCON ;IRQ mode ,nonvectored interrupt mode
ldr r1,=0x05
str r1,[r0]
ldr r1,=INTMSK
ldr r0,=0x03ffffff
str r0,[r1]
bl Main
b .
HandlerFIQ
sub sp,sp,#4
stmfd sp!,{r0}
ldr r0,=HandleFIQ
ldr r0,[r0]
str r0,[sp,#4]
ldmfd sp!,{r0,pc}
HandlerUndef
sub sp,sp,#4
stmfd sp!,{r0}
ldr r0,=HandleUndef
ldr r0,[r0]
str r0,[sp,#4]
ldmfd sp!,{r0,pc}
HandlerSWI
sub sp,sp,#4
stmfd sp!,{r0}
ldr r0,=HandleSWI
ldr r0,[r0]
str r0,[sp,#4]
ldmfd sp!,{r0,pc}
HandlerDabort
sub sp,sp,#4
stmfd sp!,{r0}
ldr r0,=HandleDabort
ldr r0,[r0]
str r0,[sp,#4]
ldmfd sp!,{r0,pc}
HandlerPabort
sub sp,sp,#4
stmfd sp!,{r0}
ldr r0,=HandlePabort
ldr r0,[r0]
str r0,[sp,#4]
ldmfd sp!,{r0,pc}
HandlerIRQ
;using I_ISPR register.
sub sp,sp,#4 ;reserved for PC
stmfd sp!,{r8-r9}
ldr r9,=I_ISPR
ldr r9,[r9]
cmp r9, #0x0
beq %F2
mov r8,#0x0
0
movs r9,r9,lsr #1
bcs %F1
add r8,r8,#4
b %B0
1
ldr r9,=HandleADC ;interrupt vector base address
add r9,r9,r8
ldr r9,[r9]
str r9,[sp,#8]
ldmfd sp!,{r8-r9,pc}
2
ldmfd sp!,{r8-r9}
add sp,sp,#4
subs pc,lr,#4
;****************************************************
;* The function for initializing stack *
;****************************************************
InitStacks
mrs r0,cpsr
bic r0,r0,#MODEMASK
orr r1,r0,#UNDEFMODE|NOINT
msr cpsr_cxsf,r1 ;UndefMode
ldr sp,=UndefStack
orr r1,r0,#ABORTMODE|NOINT
msr cpsr_cxsf,r1 ;AbortMode
ldr sp,=AbortStack
orr r1,r0,#IRQMODE|NOINT
msr cpsr_cxsf,r1 ;IRQMode
ldr sp,=IRQStack
orr r1,r0,#FIQMODE|NOINT
msr cpsr_cxsf,r1 ;FIQMode
ldr sp,=FIQStack
bic r0,r0,#MODEMASK|NOINT
orr r1,r0,#SVCMODE
msr cpsr_cxsf,r1 ;SVCMode
ldr sp,=SVCStack
mov pc,lr ;The LR register may be not valid for the mode changes.
SMRDATA
DCD 0x11001502 ;Bank0=OM[1:0],Bank1=8bit,Bank2=8bit,Bank3~Bank5=8bit,Bank6=16bit,Bank7=8bit
DCD 0x0650 ;GCS0:BOOT ROM
DCD 0x0700 ;GCS1 no use
DCD 0x0700 ;GCS2 no use
DCD 0x0700 ;GCS3 no use
DCD 0x0700 ;GCS4 no use
DCD 0x0700 ;GCS5 no use
DCD 0x18000 ;GCS6 SDRAM COLUMN ADDRESS=8BIT
DCD 0x18008 ;GCS7 no use
DCD 0x810533 ;REFRESH
DCD 0x16 ;SCLK BANKSIZE=8M
DCD 0x20 ;MRSR6 CL=2clk
DCD 0x20 ;MRSR7
AREA RamData, DATA, READWRITE
^ (_ISR_STARTADDRESS-0x20000)
UserStack # 256
SVCStack # 65536
UndefStack # 256
AbortStack # 256
IRQStack # 4096
FIQStack # 256
^ (_ISR_STARTADDRESS)
HandleReset # 4
HandleUndef # 4
HandleSWI # 4
HandlePabort # 4
HandleDabort # 4
HandleReserved # 4
HandleIRQ # 4
HandleFIQ # 4
HandleADC # 4
HandleRTC # 4
HandleUTXD1 # 4
HandleUTXD0 # 4
HandleSIO # 4
HandleIIC # 4
HandleURXD1 # 4
HandleURXD0 # 4
HandleTIMER5 # 4
HandleTIMER4 # 4
HandleTIMER3 # 4
HandleTIMER2 # 4
HandleTIMER1 # 4
HandleTIMER0 # 4
HandleUERR01 # 4
HandleWDT # 4
HandleBDMA1 # 4
HandleBDMA0 # 4
HandleZDMA1 # 4
HandleZDMA0 # 4
HandleTICK # 4
HandleEINT4567 # 4
HandleEINT3 # 4
HandleEINT2 # 4
HandleEINT1 # 4
HandleEINT0 # 4 ;0xdffff84
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