#ifndef __ASM_PPC_PROCESSOR_H#define __ASM_PPC_PROCESSOR_H/* * Default implementation of macro that returns current * instruction pointer ("program counter"). */#define current_text_addr() ({ __label__ _l; _l: &&_l;})#include <linux/config.h>#include <asm/ptrace.h>#include <asm/types.h>/* Machine State Register (MSR) Fields */#ifdef CONFIG_PPC64BRIDGE#define MSR_SF		(1<<63)#define MSR_ISF		(1<<61)#endif /* CONFIG_PPC64BRIDGE */#define MSR_UCLE        (1<<26)         /* User-mode cache lock enable (e500) */#define MSR_VEC		(1<<25)		/* Enable AltiVec(74xx) */#define MSR_SPE         (1<<25)         /* Enable SPE(e500) */#define MSR_POW		(1<<18)		/* Enable Power Management */#define MSR_WE		(1<<18)		/* Wait State Enable */#define MSR_TGPR	(1<<17)		/* TLB Update registers in use */#define MSR_CE		(1<<17)		/* Critical Interrupt Enable */#define MSR_ILE		(1<<16)		/* Interrupt Little Endian */#define MSR_EE		(1<<15)		/* External Interrupt Enable */#define MSR_PR		(1<<14)		/* Problem State / Privilege Level */#define MSR_FP		(1<<13)		/* Floating Point enable */#define MSR_ME		(1<<12)		/* Machine Check Enable */#define MSR_FE0		(1<<11)		/* Floating Exception mode 0 */#define MSR_SE		(1<<10)		/* Single Step */#define MSR_DWE         (1<<10)         /* Debug Wait Enable (4xx) */#define MSR_UBLE        (1<<10)         /* BTB lock enable (e500) */#define MSR_BE		(1<<9)		/* Branch Trace */#define MSR_DE		(1<<9) 		/* Debug Exception Enable */#define MSR_FE1		(1<<8)		/* Floating Exception mode 1 */#define MSR_IP		(1<<6)		/* Exception prefix 0x000/0xFFF */#define MSR_IR		(1<<5) 		/* Instruction Relocate */#define MSR_IS          (1<<5)          /* Book E Instruction space */#define MSR_DR		(1<<4) 		/* Data Relocate */#define MSR_DS          (1<<4)          /* Book E Data space */#define MSR_PE		(1<<3)		/* Protection Enable */#define MSR_PX		(1<<2)		/* Protection Exclusive Mode */#define MSR_PMM         (1<<2)          /* Performance monitor mark bit (e500) */#define MSR_RI		(1<<1)		/* Recoverable Exception */#define MSR_LE		(1<<0) 		/* Little Endian */#ifdef CONFIG_APUS_FAST_EXCEPT#define MSR_		MSR_ME|MSR_IP|MSR_RI#else#define MSR_		MSR_ME|MSR_RI#endif#ifndef CONFIG_E500#define MSR_KERNEL      MSR_|MSR_IR|MSR_DR#else#define MSR_KERNEL	MSR_ME#endif#define MSR_USER	MSR_KERNEL|MSR_PR|MSR_EE/* Floating Point Status and Control Register (FPSCR) Fields */#define FPSCR_FX	0x80000000	/* FPU exception summary */#define FPSCR_FEX	0x40000000	/* FPU enabled exception summary */#define FPSCR_VX	0x20000000	/* Invalid operation summary */#define FPSCR_OX	0x10000000	/* Overflow exception summary */#define FPSCR_UX	0x08000000	/* Underflow exception summary */#define FPSCR_ZX	0x04000000	/* Zero-devide exception summary */#define FPSCR_XX	0x02000000	/* Inexact exception summary */#define FPSCR_VXSNAN	0x01000000	/* Invalid op for SNaN */#define FPSCR_VXISI	0x00800000	/* Invalid op for Inv - Inv */#define FPSCR_VXIDI	0x00400000	/* Invalid op for Inv / Inv */#define FPSCR_VXZDZ	0x00200000	/* Invalid op for Zero / Zero */#define FPSCR_VXIMZ	0x00100000	/* Invalid op for Inv * Zero */#define FPSCR_VXVC	0x00080000	/* Invalid op for Compare */#define FPSCR_FR	0x00040000	/* Fraction rounded */#define FPSCR_FI	0x00020000	/* Fraction inexact */#define FPSCR_FPRF	0x0001f000	/* FPU Result Flags */#define FPSCR_FPCC	0x0000f000	/* FPU Condition Codes */#define FPSCR_VXSOFT	0x00000400	/* Invalid op for software request */#define FPSCR_VXSQRT	0x00000200	/* Invalid op for square root */#define FPSCR_VXCVI	0x00000100	/* Invalid op for integer convert */#define FPSCR_VE	0x00000080	/* Invalid op exception enable */#define FPSCR_OE	0x00000040	/* IEEE overflow exception enable */#define FPSCR_UE	0x00000020	/* IEEE underflow exception enable */#define FPSCR_ZE	0x00000010	/* IEEE zero divide exception enable */#define FPSCR_XE	0x00000008	/* FP inexact exception enable */#define FPSCR_NI	0x00000004	/* FPU non IEEE-Mode */#define FPSCR_RN	0x00000003	/* FPU rounding control *//* Special Purpose Registers (SPRNs)*/#define	SPRN_CDBCR	0x3D7	/* Cache Debug Control Register */#define	SPRN_CTR	0x009	/* Count Register */#define	SPRN_DABR	0x3F5	/* Data Address Breakpoint Register */#ifndef CONFIG_BOOKE#define	SPRN_DAC1	0x3F6	/* Data Address Compare 1 */#define	SPRN_DAC2	0x3F7	/* Data Address Compare 2 */#else#define SPRN_DAC1       0x13C   /* Book E Data Address Compare 1 */#define SPRN_DAC2       0x13D   /* Book E Data Address Compare 2 */#endif  /* CONFIG_BOOKE */#define	SPRN_DAR	0x013	/* Data Address Register */#define	SPRN_DBAT0L	0x219	/* Data BAT 0 Lower Register */#define	SPRN_DBAT0U	0x218	/* Data BAT 0 Upper Register */#define	SPRN_DBAT1L	0x21B	/* Data BAT 1 Lower Register */#define	SPRN_DBAT1U	0x21A	/* Data BAT 1 Upper Register */#define	SPRN_DBAT2L	0x21D	/* Data BAT 2 Lower Register */#define	SPRN_DBAT2U	0x21C	/* Data BAT 2 Upper Register */#define	SPRN_DBAT3L	0x21F	/* Data BAT 3 Lower Register */#define	SPRN_DBAT3U	0x21E	/* Data BAT 3 Upper Register */#define	SPRN_DBAT4L	0x239   /* Data BAT 4 Lower Register */#define	SPRN_DBAT4U	0x238   /* Data BAT 4 Upper Register */#define	SPRN_DBAT5L	0x23B   /* Data BAT 5 Lower Register */#define	SPRN_DBAT5U	0x23A   /* Data BAT 5 Upper Register */#define	SPRN_DBAT6L	0x23D   /* Data BAT 6 Lower Register */#define	SPRN_DBAT6U	0x23C   /* Data BAT 6 Upper Register */#define	SPRN_DBAT7L	0x23F   /* Data BAT 7 Lower Register */#define	SPRN_DBAT7U	0x23E   /* Data BAT 7 Lower Register */#define	SPRN_DBCR	0x3F2	/* Debug Control Regsiter */#define	  DBCR_EDM	0x80000000#define	  DBCR_IDM	0x40000000#define	  DBCR_RST(x)	(((x) & 0x3) << 28)#define	    DBCR_RST_NONE       	0#define	    DBCR_RST_CORE       	1#define	    DBCR_RST_CHIP       	2#define	    DBCR_RST_SYSTEM		3#define	  DBCR_IC	0x08000000	/* Instruction Completion Debug Evnt */#define	  DBCR_BT	0x04000000	/* Branch Taken Debug Event */#define	  DBCR_EDE	0x02000000	/* Exception Debug Event */#define	  DBCR_TDE	0x01000000	/* TRAP Debug Event */#define	  DBCR_FER	0x00F80000	/* First Events Remaining Mask */#define	  DBCR_FT	0x00040000	/* Freeze Timers on Debug Event */#define	  DBCR_IA1	0x00020000	/* Instr. Addr. Compare 1 Enable */#define	  DBCR_IA2	0x00010000	/* Instr. Addr. Compare 2 Enable */#define	  DBCR_D1R	0x00008000	/* Data Addr. Compare 1 Read Enable */#define	  DBCR_D1W	0x00004000	/* Data Addr. Compare 1 Write Enable */#define	  DBCR_D1S(x)	(((x) & 0x3) << 12)	/* Data Adrr. Compare 1 Size */#define	    DAC_BYTE	0#define	    DAC_HALF	1#define	    DAC_WORD	2#define	    DAC_QUAD	3#define	  DBCR_D2R	0x00000800	/* Data Addr. Compare 2 Read Enable */#define	  DBCR_D2W	0x00000400	/* Data Addr. Compare 2 Write Enable */#define	  DBCR_D2S(x)	(((x) & 0x3) << 8)	/* Data Addr. Compare 2 Size */#define	  DBCR_SBT	0x00000040	/* Second Branch Taken Debug Event */#define	  DBCR_SED	0x00000020	/* Second Exception Debug Event */#define	  DBCR_STD	0x00000010	/* Second Trap Debug Event */#define	  DBCR_SIA	0x00000008	/* Second IAC Enable */#define	  DBCR_SDA	0x00000004	/* Second DAC Enable */#define	  DBCR_JOI	0x00000002	/* JTAG Serial Outbound Int. Enable */#define	  DBCR_JII	0x00000001	/* JTAG Serial Inbound Int. Enable */#ifndef CONFIG_BOOKE#define SPRN_DBCR0      0x3F2           /* Debug Control Register 0 */#else#define SPRN_DBCR0      0x134           /* Book E Debug Control Register 0 */#endif /* CONFIG_BOOKE */#ifndef CONFIG_BOOKE#define	SPRN_DBCR1	0x3BD	/* Debug Control Register 1 */#define	SPRN_DBSR	0x3F0	/* Debug Status Register */#else#define SPRN_DBCR1      0x135           /* Book E Debug Control Register 1 */#define SPRN_DBSR       0x130           /* Book E Debug Status Register */#define   DBSR_IC           0x08000000  /* Book E Instruction Completion  */#define   DBSR_TIE          0x01000000  /* Book E Trap Instruction Event */#endif /* CONFIG_BOOKE */#define	SPRN_DCCR	0x3FA	/* Data Cache Cacheability Register */#define	  DCCR_NOCACHE		0	/* Noncacheable */#define	  DCCR_CACHE		1	/* Cacheable */#define	SPRN_DCMP	0x3D1	/* Data TLB Compare Register */#define	SPRN_DCWR	0x3BA	/* Data Cache Write-thru Register */#define	  DCWR_COPY		0	/* Copy-back */#define	  DCWR_WRITE		1	/* Write-through */#ifndef CONFIG_BOOKE#define	SPRN_DEAR	0x3D5	/* Data Error Address Register */#else#define SPRN_DEAR       0x03D   /* Book E Data Error Address Register */#endif /* CONFIG_BOOKE */#define	SPRN_DEC	0x016	/* Decrement Register */#define	SPRN_DMISS	0x3D0	/* Data TLB Miss Register */#define	SPRN_DSISR	0x012	/* Data Storage Interrupt Status Register */#define	SPRN_EAR	0x11A	/* External Address Register */#ifndef CONFIG_BOOKE#define	SPRN_ESR	0x3D4	/* Exception Syndrome Register */#else#define SPRN_ESR        0x03E           /* Book E Exception Syndrome Register */#endif /* CONFIG_BOOKE */#define	  ESR_IMCP	0x80000000	/* Instr. Machine Check - Protection */#define	  ESR_IMCN	0x40000000	/* Instr. Machine Check - Non-config */#define	  ESR_IMCB	0x20000000	/* Instr. Machine Check - Bus error */#define	  ESR_IMCT	0x10000000	/* Instr. Machine Check - Timeout */#define	  ESR_PIL	0x08000000	/* Program Exception - Illegal */#define	  ESR_PPR	0x04000000	/* Program Exception - Priveleged */#define	  ESR_PTR	0x02000000	/* Program Exception - Trap */#define	  ESR_DST	0x00800000	/* Storage Exception - Data miss */#define	  ESR_DIZ	0x00400000	/* Storage Exception - Zone fault */#define	SPRN_EVPR	0x3D6	/* Exception Vector Prefix Register */#define	SPRN_HASH1	0x3D2	/* Primary Hash Address Register */#define	SPRN_HASH2	0x3D3	/* Secondary Hash Address Resgister */#define	SPRN_HID0	0x3F0	/* Hardware Implementation Register 0 */#define	  HID0_EMCP	(1<<31)		/* Enable Machine Check pin */#define	  HID0_EBA	(1<<29)		/* Enable Bus Address Parity */#define	  HID0_EBD	(1<<28)		/* Enable Bus Data Parity */#define	  HID0_SBCLK	(1<<27)#define	  HID0_EICE	(1<<26)#define	  HID0_ECLK	(1<<25)#define	  HID0_PAR	(1<<24)#define	  HID0_DOZE	(1<<23)#define	  HID0_NAP	(1<<22)#define	  HID0_SLEEP	(1<<21)#define	  HID0_DPM	(1<<20)#define	  HID0_ICE	(1<<15)		/* Instruction Cache Enable */#define	  HID0_DCE	(1<<14)		/* Data Cache Enable */#define	  HID0_ILOCK	(1<<13)		/* Instruction Cache Lock */#define	  HID0_DLOCK	(1<<12)		/* Data Cache Lock */#define	  HID0_ICFI	(1<<11)		/* Instr. Cache Flash Invalidate */#define	  HID0_DCFI	(1<<10)		/* Data Cache Flash Invalidate */#define	  HID0_DCI	HID0_DCFI#define   HID0_SPD	(1<<9)		/* Speculative disable */#define   HID0_SGE	(1<<7)		/* Store Gathering Enable */#define	  HID0_SIED	HID_SGE		/* Serial Instr. Execution [Disable] */#define   HID0_DCFA	(1<<6)		/* Data Cache Flush Assist */#define   HID0_BTIC	(1<<5)		/* Branch Target Instruction Cache Enable */#define   HID0_ABE	(1<<3)		/* Address Broadcast Enable */#define	  HID0_BHTE	(1<<2)		/* Branch History Table Enable */#define	  HID0_BTCD	(1<<1)		/* Branch target cache disable */#define	SPRN_HID1	0x3F1	/* Hardware Implementation Register 1 */#define	SPRN_IABR	0x3F2	/* Instruction Address Breakpoint Register */#ifndef CONFIG_BOOKE#define	SPRN_IAC1	0x3F4	/* Instruction Address Compare 1 */#define	SPRN_IAC2	0x3F5	/* Instruction Address Compare 2 */#else#define SPRN_IAC1       0x138   /* Book E Instruction Address Compare 1 */#define SPRN_IAC2       0x139   /* Book E Instruction Address Compare 2 */#endif /* CONFIG_BOOKE */#define	SPRN_IBAT0L	0x211	/* Instruction BAT 0 Lower Register */#define	SPRN_IBAT0U	0x210	/* Instruction BAT 0 Upper Register */#define	SPRN_IBAT1L	0x213	/* Instruction BAT 1 Lower Register */#define	SPRN_IBAT1U	0x212	/* Instruction BAT 1 Upper Register */#define	SPRN_IBAT2L	0x215	/* Instruction BAT 2 Lower Register */#define	SPRN_IBAT2U	0x214	/* Instruction BAT 2 Upper Register */#define	SPRN_IBAT3L	0x217	/* Instruction BAT 3 Lower Register */#define	SPRN_IBAT3U	0x216	/* Instruction BAT 3 Upper Register */#define	SPRN_IBAT4L	0x231   /* Instruction BAT 4 Lower Register */#define	SPRN_IBAT4U	0x230   /* Instruction BAT 4 Upper Register */#define	SPRN_IBAT5L	0x233   /* Instruction BAT 5 Lower Register */#define	SPRN_IBAT5U	0x232   /* Instruction BAT 5 Upper Register */#define	SPRN_IBAT6L	0x235   /* Instruction BAT 6 Lower Register */#define	SPRN_IBAT6U	0x234   /* Instruction BAT 6 Upper Register */#define	SPRN_IBAT7L	0x237   /* Instruction BAT 7 Lower Register */#define	SPRN_IBAT7U	0x236   /* Instruction BAT 7 Upper Register */#define	SPRN_ICCR	0x3FB	/* Instruction Cache Cacheability Register */#define	  ICCR_NOCACHE		0	/* Noncacheable */#define	  ICCR_CACHE		1	/* Cacheable */#define	SPRN_ICDBDR	0x3D3	/* Instruction Cache Debug Data Register */#define	SPRN_ICMP	0x3D5	/* Instruction TLB Compare Register */#define	SPRN_ICTC	0x3FB	/* Instruction Cache Throttling Control Reg */#define	SPRN_IMISS	0x3D4	/* Instruction TLB Miss Register */#define	SPRN_IMMR	0x27E  	/* Internal Memory Map Register */#define	SPRN_L2CR	0x3F9	/* Level 2 Cache Control Regsiter */#define	SPRN_LR		0x008	/* Link Register */#define	SPRN_MMCR0	0x3B8	/* Monitor Mode Control Register 0 */#define	SPRN_MMCR1	0x3BC	/* Monitor Mode Control Register 1 */#define	SPRN_PBL1	0x3FC	/* Protection Bound Lower 1 */#define	SPRN_PBL2	0x3FE	/* Protection Bound Lower 2 */#define	SPRN_PBU1	0x3FD	/* Protection Bound Upper 1 */#define	SPRN_PBU2	0x3FF	/* Protection Bound Upper 2 */#ifndef CONFIG_BOOKE#define	SPRN_PID	0x3B1	/* Process ID */#define	SPRN_PIR	0x3FF	/* Processor Identification Register */#else#define SPRN_PID        0x030   /* Book E Process ID */#define SPRN_PIR        0x11E   /* Book E Processor Identification Register */#endif /* CONFIG_BOOKE */#define	SPRN_PIT	0x3DB	/* Programmable Interval Timer */#define	SPRN_PMC1	0x3B9	/* Performance Counter Register 1 */#define	SPRN_PMC2	0x3BA	/* Performance Counter Register 2 */#define	SPRN_PMC3	0x3BD	/* Performance Counter Register 3 */#define	SPRN_PMC4	0x3BE	/* Performance Counter Register 4 */#define	SPRN_PVR	0x11F	/* Processor Version Register */#define	SPRN_RPA	0x3D6	/* Required Physical Address Register */#define	SPRN_SDA	0x3BF	/* Sampled Data Address Register */#define	SPRN_SDR1	0x019	/* MMU Hash Base Register */#define	SPRN_SGR	0x3B9	/* Storage Guarded Register */#define	  SGR_NORMAL		0#define	  SGR_GUARDED		1#define	SPRN_SIA	0x3BB	/* Sampled Instruction Address Register */#define	SPRN_SPRG0	0x110	/* Special Purpose Register General 0 */#define	SPRN_SPRG1	0x111	/* Special Purpose Register General 1 */#define	SPRN_SPRG2	0x112	/* Special Purpose Register General 2 */#define	SPRN_SPRG3	0x113	/* Special Purpose Register General 3 */#define	SPRN_SRR0	0x01A	/* Save/Restore Register 0 */#define	SPRN_SRR1	0x01B	/* Save/Restore Register 1 */#define	SPRN_SRR2	0x3DE	/* Save/Restore Register 2 */#define	SPRN_SRR3 	0x3DF	/* Save/Restore Register 3 */#define	SPRN_TBHI	0x3DC	/* Time Base High */#define	SPRN_TBHU	0x3CC	/* Time Base High User-mode */#define	SPRN_TBLO	0x3DD	/* Time Base Low */#define	SPRN_TBLU	0x3CD	/* Time Base Low User-mode */#define	SPRN_TBRL	0x10D	/* Time Base Read Lower Register */#define	SPRN_TBRU	0x10C	/* Time Base Read Upper Register */#define	SPRN_TBWL	0x11D	/* Time Base Write Lower Register */#define	SPRN_TBWU	0x11C	/* Time Base Write Upper Register */#ifndef CONFIG_BOOKE#define	SPRN_TCR	0x3DA	/* Timer Control Register */#else#define SPRN_TCR        0x154   /* Book E Timer Control Register */#endif /* CONFIG_BOOKE */#define	  TCR_WP(x)		(((x)&0x3)<<30)	/* WDT Period */#define	    WP_2_17		0		/* 2^17 clocks */#define	    WP_2_21		1		/* 2^21 clocks */#define	    WP_2_25		2		/* 2^25 clocks */#define	    WP_2_29		3		/* 2^29 clocks */#define	  TCR_WRC(x)		(((x)&0x3)<<28)	/* WDT Reset Control */#define	    WRC_NONE		0		/* No reset will occur */#define	    WRC_CORE		1		/* Core reset will occur */#define	    WRC_CHIP		2		/* Chip reset will occur */#define	    WRC_SYSTEM		3		/* System reset will occur */#define	  TCR_WIE		0x08000000	/* WDT Interrupt Enable */#define	  TCR_PIE		0x04000000	/* PIT Interrupt Enable */#define	  TCR_FP(x)		(((x)&0x3)<<24)	/* FIT Period */#define	    FP_2_9		0		/* 2^9 clocks */#define	    FP_2_13		1		/* 2^13 clocks */#define	    FP_2_17		2		/* 2^17 clocks */#define	    FP_2_21		3		/* 2^21 clocks */#define	  TCR_FIE		0x00800000	/* FIT Interrupt Enable */#define	  TCR_ARE		0x00400000	/* Auto Reload Enable */