?? stm32f10x_tim1.c
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/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : stm32f10x_tim1.c
* Author : MCD Application Team
* Version : V1.0
* Date : 10/08/2007
* Description : This file provides all the TIM1 software functions.
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_tim1.h"
#include "stm32f10x_rcc.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* ------------ TIM1 registers bit address in the alias region ----------- */
#define TIM1_OFFSET (TIM1_BASE - PERIPH_BASE)
/* --- TIM1 CR1 Register ---*/
/* Alias word address of CEN bit */
#define CR1_OFFSET (TIM1_OFFSET + 0x00)
#define CEN_BitNumber 0x00
#define CR1_CEN_BB (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (CEN_BitNumber * 4))
/* Alias word address of UDIS bit */
#define UDIS_BitNumber 0x01
#define CR1_UDIS_BB (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (UDIS_BitNumber * 4))
/* Alias word address of URS bit */
#define URS_BitNumber 0x02
#define CR1_URS_BB (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (URS_BitNumber * 4))
/* Alias word address of OPM bit */
#define OPM_BitNumber 0x03
#define CR1_OPM_BB (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (OPM_BitNumber * 4))
/* Alias word address of ARPE bit */
#define ARPE_BitNumber 0x07
#define CR1_ARPE_BB (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (ARPE_BitNumber * 4))
/* --- TIM1 CR2 Register --- */
/* Alias word address of CCPC bit */
#define CR2_OFFSET (TIM1_OFFSET + 0x04)
#define CCPC_BitNumber 0x00
#define CR2_CCPC_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (CCPC_BitNumber * 4))
/* Alias word address of CCUS bit */
#define CCUS_BitNumber 0x02
#define CR2_CCUS_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (CCUS_BitNumber * 4))
/* Alias word address of CCDS bit */
#define CCDS_BitNumber 0x03
#define CR2_CCDS_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (CCDS_BitNumber * 4))
/* Alias word address of TI1S bit */
#define TI1S_BitNumber 0x07
#define CR2_TI1S_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (TI1S_BitNumber * 4))
/* Alias word address of OIS1 bit */
#define OIS1_BitNumber 0x08
#define CR2_OIS1_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS1_BitNumber * 4))
/* Alias word address of OIS1N bit */
#define OIS1N_BitNumber 0x09
#define CR2_OIS1N_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS1N_BitNumber * 4))
/* Alias word address of OIS2 bit */
#define OIS2_BitNumber 0x0A
#define CR2_OIS2_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS2_BitNumber * 4))
/* Alias word address of OIS2N bit */
#define OIS2N_BitNumber 0x0B
#define CR2_OIS2N_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS2N_BitNumber * 4))
/* Alias word address of OIS3 bit */
#define OIS3_BitNumber 0x0C
#define CR2_OIS3_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS3_BitNumber * 4))
/* Alias word address of OIS3N bit */
#define OIS3N_BitNumber 0x0D
#define CR2_OIS3N_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS3N_BitNumber * 4))
/* Alias word address of OIS4 bit */
#define OIS4_BitNumber 0x0E
#define CR2_OIS4_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS4_BitNumber * 4))
/* --- TIM1 SMCR Register --- */
/* Alias word address of MSM bit */
#define SMCR_OFFSET (TIM1_OFFSET + 0x08)
#define MSM_BitNumber 0x07
#define SMCR_MSM_BB (PERIPH_BB_BASE + (SMCR_OFFSET * 32) + (MSM_BitNumber * 4))
/* Alias word address of ECE bit */
#define ECE_BitNumber 0x0E
#define SMCR_ECE_BB (PERIPH_BB_BASE + (SMCR_OFFSET * 32) + (ECE_BitNumber * 4))
/* --- TIM1 EGR Register --- */
/* Alias word address of UG bit */
#define EGR_OFFSET (TIM1_OFFSET + 0x14)
#define UG_BitNumber 0x00
#define EGR_UG_BB (PERIPH_BB_BASE + (EGR_OFFSET * 32) + (UG_BitNumber * 4))
/* --- TIM1 CCER Register --- */
/* Alias word address of CC1E bit */
#define CCER_OFFSET (TIM1_OFFSET + 0x20)
#define CC1E_BitNumber 0x00
#define CCER_CC1E_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC1E_BitNumber * 4))
/* Alias word address of CC1P bit */
#define CC1P_BitNumber 0x01
#define CCER_CC1P_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC1P_BitNumber * 4))
/* Alias word address of CC1NE bit */
#define CC1NE_BitNumber 0x02
#define CCER_CC1NE_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC1NE_BitNumber * 4))
/* Alias word address of CC1NP bit */
#define CC1NP_BitNumber 0x03
#define CCER_CC1NP_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC1NP_BitNumber * 4))
/* Alias word address of CC2E bit */
#define CC2E_BitNumber 0x04
#define CCER_CC2E_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC2E_BitNumber * 4))
/* Alias word address of CC2P bit */
#define CC2P_BitNumber 0x05
#define CCER_CC2P_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC2P_BitNumber * 4))
/* Alias word address of CC2NE bit */
#define CC2NE_BitNumber 0x06
#define CCER_CC2NE_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC2NE_BitNumber * 4))
/* Alias word address of CC2NP bit */
#define CC2NP_BitNumber 0x07
#define CCER_CC2NP_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC2NP_BitNumber * 4))
/* Alias word address of CC3E bit */
#define CC3E_BitNumber 0x08
#define CCER_CC3E_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC3E_BitNumber * 4))
/* Alias word address of CC3P bit */
#define CC3P_BitNumber 0x09
#define CCER_CC3P_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC3P_BitNumber * 4))
/* Alias word address of CC3NE bit */
#define CC3NE_BitNumber 0x0A
#define CCER_CC3NE_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC3NE_BitNumber * 4))
/* Alias word address of CC3NP bit */
#define CC3NP_BitNumber 0x0B
#define CCER_CC3NP_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC3NP_BitNumber * 4))
/* Alias word address of CC4E bit */
#define CC4E_BitNumber 0x0C
#define CCER_CC4E_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC4E_BitNumber * 4))
/* Alias word address of CC4P bit */
#define CC4P_BitNumber 0x0D
#define CCER_CC4P_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC4P_BitNumber * 4))
/* --- TIM1 BDTR Register --- */
/* Alias word address of MOE bit */
#define BDTR_OFFSET (TIM1_OFFSET + 0x44)
#define MOE_BitNumber 0x0F
#define BDTR_MOE_BB (PERIPH_BB_BASE + (BDTR_OFFSET * 32) + (MOE_BitNumber * 4))
/* --- TIM1 CCMR1 Register --- */
/* Alias word address of OC1FE bit */
#define CCMR1_OFFSET (TIM1_OFFSET + 0x18)
#define OC1FE_BitNumber 0x02
#define CCMR1_OC1FE_BB (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC1FE_BitNumber * 4))
/* Alias word address of OC1PE bit */
#define OC1PE_BitNumber 0x03
#define CCMR1_OC1PE_BB (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC1PE_BitNumber * 4))
/* Alias word address of OC1CE bit */
#define OC1CE_BitNumber 0x07
#define CCMR1_OC1CE_BB (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC1CE_BitNumber * 4))
/* Alias word address of OC2FE bit */
#define OC2FE_BitNumber 0x0A
#define CCMR1_OC2FE_BB (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC2FE_BitNumber * 4))
/* Alias word address of OC2PE bit */
#define OC2PE_BitNumber 0x0B
#define CCMR1_OC2PE_BB (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC2PE_BitNumber * 4))
/* Alias word address of OC2CE bit */
#define OC2CE_BitNumber 0x0F
#define CCMR1_OC2CE_BB (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC2CE_BitNumber * 4))
/* --- TIM1 CCMR2 Register ---- */
/* Alias word address of OC3FE bit */
#define CCMR2_OFFSET (TIM1_OFFSET + 0x1C)
#define OC3FE_BitNumber 0x02
#define CCMR2_OC3FE_BB (PERIPH_BB_BASE + (CCMR2_OFFSET * 32) + (OC3FE_BitNumber * 4))
/* Alias word address of OC3PE bit */
#define OC3PE_BitNumber 0x03
#define CCMR2_OC3PE_BB (PERIPH_BB_BASE + (CCMR2_OFFSET * 32) + (OC3PE_BitNumber * 4))
/* Alias word address of OC3CE bit */
#define OC3CE_BitNumber 0x07
#define CCMR2_OC3CE_BB (PERIPH_BB_BASE + (CCMR2_OFFSET * 32) + (OC3CE_BitNumber * 4))
/* Alias word address of OC4FE bit */
#define OC4FE_BitNumber 0x0A
#define CCMR2_OC4FE_BB (PERIPH_BB_BASE + (CCMR2_OFFSET * 32) + (OC4FE_BitNumber * 4))
/* Alias word address of OC4PE bit */
#define OC4PE_BitNumber 0x0B
#define CCMR2_OC4PE_BB (PERIPH_BB_BASE + (CCMR2_OFFSET * 32) + (OC4PE_BitNumber * 4))
/* Alias word address of OC4CE bit */
#define OC4CE_BitNumber 0x0F
#define CCMR2_OC4CE_BB (PERIPH_BB_BASE + (CCMR2_OFFSET * 32) + (OC4CE_BitNumber * 4))
/* --------------------- TIM1 registers bit mask ------------------------- */
/* TIM1 CR1 Mask */
#define CR1_CounterMode_Mask ((u16)0x039F)
#define CR1_CKD_Mask ((u16)0x00FF)
/* TIM1 CR2 Mask */
#define CR2_MMS_Mask ((u16)0x0080)
/* TIM1 SMCR Mask */
#define SMCR_SMS_Mask ((u16)0xFFF0)
#define SMCR_ETR_Mask ((u16)0x40F7)
#define SMCR_TS_Mask ((u16)0xFF87)
#define SMCR_ECE_Set ((u16)0x0001)
/* TIM1 CCMRx Mask */
#define CCMR_CC13S_Mask ((u16)0xFFFC)
#define CCMR_CC24S_Mask ((u16)0xFCFF)
#define CCMR_TI13Direct_Set ((u16)0x0001)
#define CCMR_TI24Direct_Set ((u16)0x0100)
#define CCMR_OCM13_Mask ((u16)0x7F0F)
#define CCMR_OCM24_Mask ((u16)0x0F7F)
#define CCMR_IC13PSC_Mask ((u16)0xFFF3)
#define CCMR_IC24PSC_Mask ((u16)0xF3FF)
#define CCMR_IC13F_Mask ((u16)0xFF0F)
#define CCMR_IC24F_Mask ((u16)0x0FFF)
#define OC13Mode_Mask ((u16)0xFF00)
#define OC24Mode_Mask ((u16)0x00FF)
/* TIM1 CCER Set/Reset Bit */
#define CCER_CCE_Set ((u16)0x0001)
#define CCER_CCE_Reset ((u16)0x0000)
/* TIM1 DMA Mask */
#define DCR_DMA_Mask ((u16)0x0000)
/* TIM1 private Masks */
#define TIM1_Period_Reset_Mask ((u16)0xFFFF)
#define TIM1_Prescaler_Reset_Mask ((u16)0x0000)
#define TIM1_RepetitionCounter_Reset_Mask ((u16)0x0000)
#define TIM1_Pulse_Reset_Mask ((u16)0x0000)
#define TIM1_ICFilter_Mask ((u8)0x00)
#define TIM1_DeadTime_Reset_Mask ((u16)0x0000)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
static void TI1_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,
u8 TIM1_ICFilter);
static void TI2_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,
u8 TIM1_ICFilter);
static void TI3_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,
u8 TIM1_ICFilter);
static void TI4_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,
u8 TIM1_ICFilter);
/*******************************************************************************
* Function Name : TIM1_DeInit
* Description : Deinitializes the TIM1 peripheral registers to their default
* reset values.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void TIM1_DeInit(void)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
}
/*******************************************************************************
* Function Name : TIM1_TimeBaseInit
* Description : Initializes the TIM1 Time Base Unit according to the specified
* parameters in the TIM1_TimeBaseInitStruct.
* Input : - TIM1_TimeBaseInitStruct: pointer to a TIM1_TimeBaseInitTypeDef
* structure that contains the configuration information for
* the specified TIM1 peripheral.
* Output : None
* Return : None
*******************************************************************************/
void TIM1_TimeBaseInit(TIM1_TimeBaseInitTypeDef* TIM1_TimeBaseInitStruct)
{
/* Check the parameters */
assert_param(IS_TIM1_COUNTER_MODE(TIM1_TimeBaseInitStruct->TIM1_CounterMode));
assert_param(IS_TIM1_CKD_DIV(TIM1_TimeBaseInitStruct->TIM1_ClockDivision));
/* Set the Autoreload value */
TIM1->ARR = TIM1_TimeBaseInitStruct->TIM1_Period ;
/* Set the Prescaler value */
TIM1->PSC = TIM1_TimeBaseInitStruct->TIM1_Prescaler;
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