//*----------------------------------------------------------------------------
//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
//*----------------------------------------------------------------------------
//* The software is delivered "AS IS" without warranty or condition of any
//* kind, either express, implied or statutory. This includes without
//* limitation any warranty or condition with respect to merchantability or
//* fitness for any particular purpose, or against the infringements of
//* intellectual property rights of others.
//*----------------------------------------------------------------------------
//* File Name           : Cache.c
//* Object              : Common CACHE operations
//* Creation            : JPP  06/JUN/2003
//*----------------------------------------------------------------------------

//*----------------------------------------------------------------------------
//* \fn    AT91F_CleanDCache
//* \brief Clean and invalidate D Cache
//*----------------------------------------------------------------------------
void AT91F_CleanDCache()
{
	register char seg, index;
	for (seg = 0; seg < 8; ++seg) {
		for (index = 0; index < 64; ++index) {
			AT91F_ARM_CleanDCacheIDX((index << 26) | (seg << 5));
		}
	}
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ResetICache
//* \brief Reset I Cache (Should be run from a non cachable area)
//*----------------------------------------------------------------------------
void AT91F_ResetICache()
{
	// Flush I TLB
	AT91F_ARM_InvalidateITLB();
	// Flush I cache
	AT91F_ARM_InvalidateICache();
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ResetDCache
//* \brief Reset D Cache (Should be run from a non cachable area)
//*----------------------------------------------------------------------------
void AT91F_ResetDCache()
{
	// Achieve pending write operations
	AT91F_CleanDCache();
	// Flush write buffers
	AT91F_ARM_DrainWriteBuffer();
	// Flush D TLB
	AT91F_ARM_InvalidateDTLB();
	// Flush D cache
	AT91F_ARM_InvalidateDCache();
}


//*----------------------------------------------------------------------------
//* \fn    AT91F_EnableICache
//* \brief Enable I Cache
//*----------------------------------------------------------------------------
void AT91F_EnableICache()
{
	unsigned int ctl;

	ctl = AT91F_ARM_ReadControl();
	ctl |= (1 << 12);
	AT91F_ARM_WriteControl(ctl);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_DisableICache
//* \brief Disable I Cache
//*----------------------------------------------------------------------------
void AT91F_DisableICache()
{
	unsigned int ctl;

	ctl = AT91F_ARM_ReadControl();
	ctl &= ~(1 << 12);
	AT91F_ARM_WriteControl(ctl);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_EnableDCache
//* \brief Enable D Cache
//*----------------------------------------------------------------------------
void AT91F_EnableDCache()
{
	unsigned int ctl;

	ctl = AT91F_ARM_ReadControl();
	ctl |= (1 << 2);
	AT91F_ARM_WriteControl(ctl);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_DisableDCache
//* \brief Disable D Cache
//*----------------------------------------------------------------------------
void AT91F_DisableDCache()
{
	unsigned int ctl;

	ctl = AT91F_ARM_ReadControl();
	ctl &= ~(1 << 2);
	AT91F_ARM_WriteControl(ctl);
}