MEMORY
{
    PAGE 0 :   VECS   : origin =    0h , length =   040h   /* VECTORS */
	           PROG   : origin =   40h , length = 07f00h   /* PROGRAM */

    PAGE 1 :   MMRS   : origin =    0h , length =   060h   /* MMRS    */
               B2     : origin = 0060h , length =   020h   /* DARAM   */
               B0     : origin = 0200h , length =  0100h   /* DARAM   */
               B1     : origin = 0300h , length =  0100h   /* DARAM   */
               SARAM  : origin =0800h  ,  length  =0800h
               DATA   : origin = 8000h , length =  8000h   /* XDM     */
}

   
/*--------------------------------------------------------------------*/
/* SECTIONS ALLOCATION                                                */
/*--------------------------------------------------------------------*/
SECTIONS
{
    .vectors : { } > VECS      PAGE 0   /* Interrupt vector table     */
    .reset   : { } > VECS      PAGE 0   /* Reset code                 */
    .start   : { } > PROG      PAGE 0   /* Code                       */
    .table   : { } > PROG      PAGE 0   /* Code                       */
    .text    : { } > PROG      PAGE 0   /* Code                       */
    .mmrs    : { } > MMRS      PAGE 1   /* Memory mapped registers    */
    .bss     : { } > SARAM     PAGE 1   /* Block B2                   */
    .data    : { } > SARAM     PAGE 1   /* Initialization data tables */
    .cinit   : { } > PROG      PAGE 0   /* Block B2                   */
    .blk3    : { } > DATA      PAGE 1   /* External data memory       */
}