?? c4exa1a.mdl
字號(hào):
Model {
Name "c4exa1a"
Version 4.00
SampleTimeColors off
LibraryLinkDisplay "none"
WideLines off
ShowLineDimensions off
ShowPortDataTypes off
ShowStorageClass off
ExecutionOrder off
RecordCoverage off
CovPath "/"
CovSaveName "covdata"
CovMetricSettings "dw"
CovNameIncrementing off
CovHtmlReporting on
BlockNameDataTip off
BlockParametersDataTip off
BlockDescriptionStringDataTip off
ToolBar on
StatusBar on
BrowserShowLibraryLinks off
BrowserLookUnderMasks off
Created "Sat Sep 08 21:47:18 2001"
UpdateHistory "UpdateHistoryNever"
ModifiedByFormat "%<Auto>"
ModifiedDateFormat "%<Auto>"
LastModifiedDate "Sun Sep 23 02:56:01 2001"
ModelVersionFormat "1.%<AutoIncrement:4>"
ConfigurationManager "None"
SimParamPage "Solver"
StartTime "0.0"
StopTime "10.0"
SolverMode "Auto"
Solver "ode45"
RelTol "1e-3"
AbsTol "auto"
Refine "1"
MaxStep "auto"
MinStep "auto"
MaxNumMinSteps "-1"
InitialStep "auto"
FixedStep "auto"
MaxOrder 5
OutputOption "RefineOutputTimes"
OutputTimes "[]"
LoadExternalInput off
ExternalInput "[t, u]"
SaveTime on
TimeSaveName "tout"
SaveState off
StateSaveName "xout"
SaveOutput on
OutputSaveName "yout"
LoadInitialState off
InitialState "xInitial"
SaveFinalState off
FinalStateName "xFinal"
SaveFormat "Array"
LimitDataPoints on
MaxDataPoints "1000"
Decimation "1"
AlgebraicLoopMsg "warning"
MinStepSizeMsg "warning"
UnconnectedInputMsg "warning"
UnconnectedOutputMsg "warning"
UnconnectedLineMsg "warning"
InheritedTsInSrcMsg "warning"
SingleTaskRateTransMsg "none"
MultiTaskRateTransMsg "error"
IntegerOverflowMsg "warning"
CheckForMatrixSingularity "none"
UnnecessaryDatatypeConvMsg "none"
Int32ToFloatConvMsg "warning"
InvalidFcnCallConnMsg "error"
SignalLabelMismatchMsg "none"
LinearizationMsg "none"
VectorMatrixConversionMsg "none"
SfunCompatibilityCheckMsg "none"
BlockPriorityViolationMsg "warning"
ArrayBoundsChecking "none"
ConsistencyChecking "none"
ZeroCross on
Profile off
SimulationMode "normal"
RTWSystemTargetFile "grt.tlc"
RTWInlineParameters off
RTWRetainRTWFile off
RTWTemplateMakefile "grt_default_tmf"
RTWMakeCommand "make_rtw"
RTWGenerateCodeOnly off
TLCProfiler off
TLCDebug off
TLCCoverage off
AccelSystemTargetFile "accel.tlc"
AccelTemplateMakefile "accel_default_tmf"
AccelMakeCommand "make_rtw"
TryForcingSFcnDF off
ExtModeMexFile "ext_comm"
ExtModeBatchMode off
ExtModeTrigType "manual"
ExtModeTrigMode "normal"
ExtModeTrigPort "1"
ExtModeTrigElement "any"
ExtModeTrigDuration 1000
ExtModeTrigHoldOff 0
ExtModeTrigDelay 0
ExtModeTrigDirection "rising"
ExtModeTrigLevel 0
ExtModeArchiveMode "off"
ExtModeAutoIncOneShot off
ExtModeIncDirWhenArm off
ExtModeAddSuffixToVar off
ExtModeWriteAllDataToWs off
ExtModeArmWhenConnect on
ExtModeSkipDownloadWhenConnect off
ExtModeLogAll on
ExtModeAutoUpdateStatusClock on
OptimizeBlockIOStorage on
BufferReuse on
ParameterPooling on
BlockReductionOpt on
RTWExpressionDepthLimit 5
BooleanDataType off
BlockDefaults {
Orientation "right"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
ShowName on
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "c4exa1a"
Location [333, 373, 735, 486]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "automatic"
PaperOrientation "portrait"
PaperPositionMode "auto"
PaperType "a4letter"
PaperUnits "centimeters"
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
Name "In1"
Position [25, 33, 55, 47]
Port "1"
LatchInput off
Interpolate on
}
Block {
BlockType Sum
Name "Sum"
Ports [2, 1]
Position [90, 30, 110, 50]
ShowName off
IconShape "round"
Inputs "|+-"
SaturateOnIntegerOverflow on
}
Block {
BlockType TransferFcn
Name "Transfer Fcn"
Position [145, 22, 205, 58]
Numerator "[1]"
Denominator "[1 1]"
AbsoluteTolerance "auto"
Realization "auto"
}
Block {
BlockType TransportDelay
Name "Transport\nDelay"
Position [255, 25, 285, 55]
DelayTime "1"
InitialInput "0"
BufferSize "1024"
PadeOrder "0"
}
Block {
BlockType Outport
Name "Out1"
Position [350, 33, 380, 47]
Port "1"
OutputWhenDisabled "held"
InitialOutput "[]"
}
Line {
SrcBlock "Transfer Fcn"
SrcPort 1
DstBlock "Transport\nDelay"
DstPort 1
}
Line {
SrcBlock "Transport\nDelay"
SrcPort 1
Points [0, 0; 20, 0]
Branch {
DstBlock "Out1"
DstPort 1
}
Branch {
Points [0, 60; -210, 0]
DstBlock "Sum"
DstPort 2
}
}
Line {
SrcBlock "Sum"
SrcPort 1
DstBlock "Transfer Fcn"
DstPort 1
}
Line {
SrcBlock "In1"
SrcPort 1
DstBlock "Sum"
DstPort 1
}
Annotation {
Position [50, 82]
Text "c4exa1a.mdl"
FontName "Arial"
FontSize 12
FontWeight "bold"
}
}
}
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