?? rectifier.asm
字號:
**************************************
**File name: Rectifier.asm
**************************************
.include "F2407REGS.H"
.include "ext_refs.h"
.def _c_int0
.def GISR1,PDPINT_A
.def GISR2,T1UFINT,T1PINT,T3PINT
.def PHANTOM,GISR4,CMP3INT
.ref PVECTORS
.ref PDP ;保護(hù)延時計數(shù)
.text
_c_int0:
NOP
CALL INIT_SYS ;調(diào)用初始化系統(tǒng)函數(shù)
CALL INIT_PWM ;調(diào)用初始化PWM函數(shù)
CALL INIT_AD ;調(diào)用初始化AD函數(shù)
CALL INIT_THETA ;調(diào)用初始化相位檢測函數(shù)
CALL INIT_VOLTAGE_PI_REG
CALL CLARKE_INIT
CALL init_i_pi_reg
LDP #N
SPLK #390,N
CLRC INTM ;開總中斷
HALT:
NOP
NOP
LDP #N
LACL N
BCND HALT,NEQ
SPLK #147BH,D_THETA ;Q13 0.64*2^13
START:
LDP #GPTCONA>>7 ;裝載事件管理器A的頁地址
LACL T1CON
OR #040H
SACL T1CON ;使能定時器1
LDP #GPTCONB>>7 ;裝載事件管理器B的頁地址
LACL T4CON
OR #040H
SACL T4CON ;使能定時器4
LOOP:
NOP
NOP
CALL AD_SAMPLE
NOP
B LOOP
*************************************
****Compare int and timer1 period&underflow int
*************************************
GISR2:
NOP
MAR *,AR0
MAR *+
SST #1,*+
SST #0,*+
SACH *+
SACL *+
SETC SXM
LDP #EVAIFRA>>7
LACL EVAIFRA
SACL EVAIFRA
LDP #0E0H
LACC PIVR,1
ADD #PVECTORS
BACC
T3PINT:
NOP
LDP #COMCONA>>7 ;PWM輸出引腳解除高阻
LACL COMCONA
OR #0200H
SACL COMCONA
LDP #DP_PF2
SPLK 0,EVBIMRA ;禁止定時器周期中斷
LDP #PDP
SPLK #1H,PDP
B GISR2_RET
NOP
T1UFINT:
T1PINT:
NOP
CALL TEST ;For test
**************************************************
****The sample of the current fordback ia,ib
;and the dc voltage fordback Udc
**************************************************
CALL AD_SAMPLE
;*************************************************
****Calculate the sin_theta and cos_theta
**************************************************
CALL SIN_COS
CALL TEST ;For test
**************************************************
**** The PI regulator of voltage loop
**************************************************
LDP #Udc_fdb
BLDD #Udc,Udc_fdb
CALL VOLTAGE_PI_REG
**************************************************
****Clarke converter
;a,b,c-axis-->alfa,beta-axis
**************************************************
LDP #i_a
BLDD #Ia,i_a
BLDD #Ib,i_b
BLDD #IA,i_a ;For test
BLDD #IB,i_b ;For test
CALL CLARKE
**************************************************
****Park converter
;alfa,beta-axis-->d,q-axis
**************************************************
LDP #park_alfa
BLDD #i_alfa,park_alfa
BLDD #i_beta,park_beta
BLDD #SIN_THETA,sin
BLDD #COS_THETA,cos
CALL PARK
**************************************************
****The PI regulator of current loop
;contain the d-axis and q-axis PI regulator
**************************************************
LDP #id_fdb
BLDD #park_d,id_fdb
BLDD #Udc_out,id_ref
SPLK #0600H,id_ref ;for test,Q9 6*2^9
BLDD #park_q,iq_fdb
CALL i_pi_reg
**************************************************
****Inverse park convertor
**************************************************
LDP #ipark_d
BLDD #ud_out,ipark_d
BLDD #uq_out,ipark_q
BLDD #park_d,ipark_d ;for test
BLDD #park_q,ipark_q ;for test
splk #1900h,ipark_d ;for test
splk #0h,ipark_q ;for test
BLDD #SIN_THETA,sin_th
BLDD #COS_THETA,cos_th
CALL I_PARK
**************************************************
****SVPWM GENERATE
**************************************************
LDP #Ualfa
BLDD #ipark_alfa,Ualfa
BLDD #ipark_beta,Ubeta
CALL SVPWM_GEN
**************************************************
****for test
**************************************************
LDP #cos
LACL sin
LDP #ud_out
LACL ud_out
LDP #IB
LACL IA
LDP #i_alfa
LACL i_alfa
LDP #park_d
LACL park_d
LDP #i_a
LACL i_a
LDP #ipark_alfa
LACL ipark_beta ;Ubeta;
LDP #Ia
LACL Ib
LDP #Udc_out
LACL Udc_out
CALL DATA_CACHE
LDP #park_d
LACL park_d
LDP #id_fdb
LACL id_fdb
CALL DATA_CACHE
GISR2_RET:
NOP
MAR *,AR0
MAR *-
LACL *-
ADD *-,16
LST #0,*-
LST #1,*-
CLRC INTM
NOP
RET
*************************************
****功率保護(hù)處理中斷子程序
*************************************
GISR1: ;保護(hù)延時程序
NOP
MAR *,AR0
MAR *+
SST #1,*+
SST #0,*+
SACH *+
SACL *+
SETC SXM
LDP #EVAIFRA>>7
LACL EVAIFRA
SACL EVAIFRA
LDP #0E0H
LACC PIVR,1
ADD #PVECTORS
BACC
PDPINT_A:
NOP
LDP #DP_EVB ;指向7500h~7580h區(qū)
SPLK #2000H,GPTCONB ;不使能比較操作
SPLK #2000,T3PR ;設(shè)置定時器3周期寄存器為2000個cpu周期
SPLK #0,T3CNT ;周期寄存器加載影子寄存器值
SPLK #904CH,T3CON ;1倍頻 ;通用定時器3使能
SPLK #080H,EVBIMRA ;使能定時器3周期中斷
SPLK #0FFFFH,EVBIFRA ;清EVB全部中斷標(biāo)志
LDP #PDP
LACL PDP
SUB #1H
SACL PDP
BCND GISR1_RET,EQ
LDP #COMCONA>>7 ;PWM輸出引腳解除禁止
LACL COMCONA
OR #0200H
SACL COMCONA
GISR1_RET:
MAR *,AR0
MAR *-
LACL *-
ADD *-,16
LST #0,*-
LST #1,*-
CLRC INTM
NOP
RET
*****************************************
***INT4 CMP3INT
*****************************************
GISR4:
NOP
MAR *,AR0
MAR *+
SST #1,*+
SST #0,*+
SACH *+
SACL *+
SETC SXM
LDP #EVAIFRA>>7
LACL EVAIFRC
SACL EVAIFRC
LDP #0E0H
LACC PIVR,1
ADD #PVECTORS
BACC
CMP3INT:
NOP
CALL THETA_GET
GISR4_RET:
MAR *,AR0
MAR *-
LACL *-
ADD *-,16
LST #0,*-
LST #1,*-
CLRC INTM
NOP
RET
PHANTOM:
NOP
KICK_DOG
CLRC INTM
NOP
RET
END?? 快捷鍵說明
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