?? asm_defs.inc
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;************************************************************************
;*
;* Copyright Mentor Graphics Corporation 2002
;* All Rights Reserved.
;*
;* THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS
;* THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS
;* SUBJECT TO LICENSE TERMS.
;*
;************************************************************************
;************************************************************************
;*
;* FILE NAME VERSION
;*
;* asm_defs.inc Nucleus PLUS\ARM925\Code Composer 1.14.1
;*
;* COMPONENT
;*
;* IN - Initialization
;*
;* DESCRIPTION
;*
;* This file contains the target processor dependent initialization
;* values used in int.s, tct.s, and tmt.s
;*
;* HISTORY
;*
;* NAME DATE REMARKS
;*
;* B. Ronquillo 08-28-2002 Released version 1.13.1
;*
;************************************************************************
;**********************************
;* BOARD INITIALIZATION CONSTANTS *
;**********************************
; Begin define constants used in low-level initialization.
LOCKOUT .equ 00C0h ; Interrupt lockout value
LOCK_MSK .equ 00C0h ; Interrupt lockout mask value
MODE_MASK .equ 001Fh ; Processor Mode Mask
SUP_MODE .equ 0013h ; Supervisor Mode (SVC)
IRQ_MODE .equ 0012h ; Interrupt Mode (IRQ)
IRQ_MODE_OR_LOCKOUT .equ 00D2h ; Combined IRQ_MODE OR'ed with LOCKOUT
FIQ_MODE .equ 0011h ; Fast Interrupt Mode (FIQ)
IRQ_BIT .equ 0080h ; Interrupt bit of CPSR and SPSR
FIQ_BIT .equ 0040h ; Interrupt bit of CPSR and SPSR
IRQ_BIT_OR_FIQ_BIT .equ 00C0h ; IRQ or FIQ interrupt bit of CPSR and SPSR
IRQStatus .equ 0000h
IRQ_STACK_SIZE .equ 128 ; Number of bytes in IRQ stack
; -Note that the IRQ interrupt,
; by default, is managed by
; Nucleus PLUS. Only several
; words are actually used. The
; system stack is what will
; actually be used for Nuclues
; PLUS managed IRQ interrupts.
FIQ_STACK_SIZE .equ 128 ; Number of bytes in FIQ stack.
; This value is application
; specific. By default, Nucleus
; does not manage FIQ interrupts
; and furthermore, leaves them
; enabled virtually all the time.
IRQ_CLEAR_OFFSET .equ 0x0 ; Clears IRQ register
FIQ_CLEAR_OFFSET .equ 0x1 ; Clears FIQ register
;*****************************
;* NUCLEUS SYSTEM CONSTANTS *
;*****************************
SYSTEM_STACK_SIZE .equ 1024 ; Define the system stack size
HISR_STACK_SIZE .equ 2048 ; Define timer HISR stack size
HISR_PRIORITY .equ 2 ; Timer HISR priority (values from
; 0 to 2, where 0 is highest)
;*****************************
;* BOARD INTERRUPT CONSTANTS *
;*****************************
INT_CNTRL_BASE_1 .word 0xFFFECB00 ; Base address for interrupt handler 1
INT_CNTRL_BASE_2 .word 0xFFFE0000 ; Base address for interrupt handler 2
; Interrupt Controller Registers (page 6-17, 18 of the
; OMAP Dual Core Processor Technical Reference Manual)
INT_CNTRL_ITR .equ 00h ; (R/W)Interrupt Input Register
INT_CNTRL_MIR .equ 04h ; (R/W)Mask Interrupt Register
INT_CNTRL_SIR_IRQ_CODE .equ 10h ; (R)Source IRQ Register
INT_CNTRL_SIR_FIQ_CODE .equ 14h ; (R)Source FIQ Register
INT_CNTRL_CONTROL_REG .equ 18h ; (R/W)Interrupt Control Register
INT_CNTRL_ILR0 .equ 1Ch ; (R/W)Interrupt Level Register 0
INT_CNTRL_ILR1 .equ 20h ; (R/W)Interrupt Level Register 1
INT_CNTRL_ILR2 .equ 24h ; (R/W)Interrupt Level Register 2
INT_CNTRL_ILR3 .equ 28h ; (R/W)Interrupt Level Register 3
INT_CNTRL_ILR4 .equ 2Ch ; (R/W)Interrupt Level Register 4
INT_CNTRL_ILR5 .equ 30h ; (R/W)Interrupt Level Register 5
INT_CNTRL_ILR6 .equ 34h ; (R/W)Interrupt Level Register 6
INT_CNTRL_ILR7 .equ 38h ; (R/W)Interrupt Level Register 7
INT_CNTRL_ILR8 .equ 3Ch ; (R/W)Interrupt Level Register 8
INT_CNTRL_ILR9 .equ 40h ; (R/W)Interrupt Level Register 9
INT_CNTRL_ILR10 .equ 44h ; (R/W)Interrupt Level Register 10
INT_CNTRL_ILR11 .equ 48h ; (R/W)Interrupt Level Register 11
INT_CNTRL_ILR12 .equ 4Ch ; (R/W)Interrupt Level Register 12
INT_CNTRL_ILR13 .equ 50h ; (R/W)Interrupt Level Register 13
INT_CNTRL_ILR14 .equ 54h ; (R/W)Interrupt Level Register 14
INT_CNTRL_ILR15 .equ 58h ; (R/W)Interrupt Level Register 15
INT_CNTRL_ILR16 .equ 5Ch ; (R/W)Interrupt Level Register 16
INT_CNTRL_ILR17 .equ 60h ; (R/W)Interrupt Level Register 17
INT_CNTRL_ILR18 .equ 64h ; (R/W)Interrupt Level Register 18
INT_CNTRL_ILR19 .equ 68h ; (R/W)Interrupt Level Register 19
INT_CNTRL_ILR20 .equ 6Ch ; (R/W)Interrupt Level Register 20
INT_CNTRL_ILR21 .equ 70h ; (R/W)Interrupt Level Register 21
INT_CNTRL_ILR22 .equ 74h ; (R/W)Interrupt Level Register 22
INT_CNTRL_ILR23 .equ 78h ; (R/W)Interrupt Level Register 23
INT_CNTRL_ILR24 .equ 7Ch ; (R/W)Interrupt Level Register 24
INT_CNTRL_ILR25 .equ 80h ; (R/W)Interrupt Level Register 25
INT_CNTRL_ILR26 .equ 84h ; (R/W)Interrupt Level Register 26
INT_CNTRL_ILR27 .equ 88h ; (R/W)Interrupt Level Register 27
INT_CNTRL_ILR28 .equ 8Ch ; (R/W)Interrupt Level Register 28
INT_CNTRL_ILR29 .equ 90h ; (R/W)Interrupt Level Register 29
INT_CNTRL_ILR30 .equ 94h ; (R/W)Interrupt Level Register 30
INT_CNTRL_ILR31 .equ 98h ; (R/W)Interrupt Level Register 31
INT_CNTRL_ISR .equ 9Ch ; (R/W)Software Interrupt Set Register
INTERRUPTS_ADDR .equ 00000000h ; Begining address for all handlers
; Defining vectors from ARM Peripherals Interrupt Mapping (page 6-14,15 of the
; OMAP Dual Core Processor Technical Reference Manual)
; Level 1 Interrupt Handler
INT_IRQ0_LEVEL2 .equ 0 ; Level 2 Interrupt Handler IRQ
INT_IRQ1_Camera .equ 1 ; Camera Interrupt
INT_IRQ2_RESERVED .equ 2 ; RESERVED
INT_IRQ3_EXT_FIQ .equ 3 ; External FIQ Interrupt
INT_IRQ4_McBSP2_TX .equ 4 ; McBSP2 SPI TX Interrupt
INT_IRQ5_McBSP2_RX .equ 5 ; McBSP2 SPI RX Interrupt
INT_IRQ6_RTDX .equ 6 ; RTDX Interrupt
INT_IRQ7_DSP_MMU_ABORT .equ 7 ; DSP MMU Abort Interrupt
INT_IRQ8_HOST_INT .equ 8 ; Host Interrupt
INT_IRQ9_ABORT .equ 9 ; IRQ Abort Interrupt
INT_IRQ10_DSP_MLBX1 .equ 10 ; IRQ DSP Mailbox 1 Interrupt
INT_IRQ11_DSP_MLBX2 .equ 11 ; IRQ DSP Mailbox 2 Interrupt
INT_IRQ12_RESERVED .equ 12 ; RESERVED
INT_IRQ13_BRDG_PVT .equ 13 ; IRQ TIPB Bridge Private Interrupt
INT_IRQ14_GPIO .equ 14 ; IRQ General Purpose I/O Interrupt
INT_IRQ15_UART3 .equ 15 ; IRQ UART3 Interrupt
INT_IRQ16_TIMER3 .equ 16 ; Timer 3 Interrupt
INT_IRQ17_LB_MMU .equ 17 ; Local Bus Memory Management Unit Interrupt
INT_IRQ18_RESERVED .equ 18 ; RESERVED
INT_IRQ19_CH0_CH6 .equ 19 ; DMA Channel 0 thru Channel 6 Interrupt
INT_IRQ20_CH1_CH7 .equ 20 ; DMA Channel 1 thru Channel 7 Interrupt
INT_IRQ21_CH2_CH8 .equ 21 ; DMA Channel 2 thru Channel 8 Interrupt
INT_IRQ22_CH3 .equ 22 ; DMA Channel 3 Interrupt
INT_IRQ23_CH4 .equ 23 ; DMA Channel 4 Interrupt
INT_IRQ24_CH5 .equ 24 ; DMA Channel 5 Interrupt
INT_IRQ25_CH_LCD .equ 25 ; DMA LCD Interrupt
INT_IRQ26_TIMER1 .equ 26 ; Timer 1 Interrupt (Set as FIQ Timer)
INT_IRQ27_WD_TIMER .equ 27 ; Watchdog Timer Interrupt
INT_IRQ28_BRDG_PBC .equ 28 ; IRQ TIPB Bridge Public Interrupt
INT_IRQ29_LOC_BUS_IF .equ 29 ; Local Bus I/F
INT_IRQ30_TIMER2 .equ 30 ; Timer 2 Interrupt (Set as Nucleus Timer)
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