INT_IRQ31_LCD_CTRL          .equ    31    ; LCD Control Interrupt

; Level 2 Interrupt Handler (under MPU Interrupt Handlers)
INT_IRQ32_FAC               .equ    32    ; Hardware Errors
INT_IRQ33_KEYPAD            .equ    33    ; Keypad Interrupt
INT_IRQ34_MICROWARE_TX      .equ    34    ; Microware Tx Interrupt  
INT_IRQ35_MICROWARE_RX      .equ    35    ; Microware Rx Interrupt  
INT_IRQ36_I2C               .equ    36    ; I2C Interrupt  
INT_IRQ37_MPUIO             .equ    37    ; Microprocessor Unit I/O Interrupt  
INT_IRQ38_USB_HHC_1         .equ    38    ; USB HHC 1 Interrupt  
INT_IRQ39_USB_HHC_2         .equ    39    ; USB HHC 2 Interrupt
INT_IRQ40_RESERVED          .equ    40    ; Reserved
INT_IRQ41_RESERVED          .equ    41    ; Reserved
INT_IRQ42_McBSP3_TX         .equ    42    ; McBSP3 Transmit Interrupt  
INT_IRQ43_McBSP3_RX         .equ    43    ; McBSP3 Receive Interrupt  
INT_IRQ44_McBSP1_TX         .equ    44    ; McBSP1 Transmit Interrupt  
INT_IRQ45_McBSP1_RX         .equ    45    ; McBSP1 Receive Interrupt  
INT_IRQ46_UART1             .equ    46    ; UART 1 Interrupt (Bluetooth)  
INT_IRQ47_UART2             .equ    47    ; UART 2 Interrupt  
INT_IRQ48_MCSI1_FE          .equ    48    ; MCSI 1 FE Interrupt  
INT_IRQ49_MCSI2_FE          .equ    49    ; MCSI 2 FE Interrupt
INT_IRQ50_RESERVED          .equ    50    ; RESERVED
INT_IRQ51_RESERVED          .equ    51    ; RESERVED
INT_IRQ52_USB_FUN_GEN       .equ    52    ; USB Function Generator Interrupt  
INT_IRQ53_1_WIRE            .equ    53    ; 1 Wire Interrupt
INT_IRQ54_32K_TIMER         .equ    54    ; 32K Timer
INT_IRQ55_MMC               .equ    55    ; MMC Interrupt  
INT_IRQ56_ULPD              .equ    56    ; ULPD GuagingInterrupt
INT_IRQ57_RTC_TIMER         .equ    57    ; RTC Timer Interrupt
INT_IRQ58_RTC_ALARM         .equ    58    ; RTC Alarm Interrupt
INT_IRQ59_RESERVED          .equ    59    ; Reserved
INT_IRQ60_DSP_MMU           .equ    60    ; DSP MMU Interrupt  
INT_IRQ61_USB_ISO           .equ    61    ; USB Function ISO On Interrupt  
INT_IRQ62_USB_NON_ISO       .equ    62    ; USB Function NON ISO On Interrupt  
INT_IRQ63_McBSP2_RX_OVER    .equ    63    ; McBSP2 Receive Overflow Interrupt  

;**********************************
;* NUCLEUS FIQ TIMER CONSTANTS    *
;**********************************
; Page 6-5,6 of the OMAP Dual Core Processor Technical Reference Manual
; Based off TIMER 1
FIQ_TIMER_BASE              .word 0xFFFEC500        ; Define base for all timer registers
FIQ_LOAD_TIM_OFFSET         .equ  0x04              ; Offset of timer load register from base
FIQ_TIMER_ENABLE            .equ  0x20              ; Must set this before a timer 
                                                    ; is used (CNTL TIMER Reg)
FIQ_TIMER_PTV               .equ  0x00000000        ; Prescale clock by 2
FIQ_TIMER_ST                .equ  0x00000001        ; Bit 0 to start timer
FIQ_TIMER_AR                .equ  0x00000002        ; Bit 1 to auto-reload
FIQ_TIMER_CLOCK             .equ  84000000          ; Clock used by timer
FIQ_TIMER_PRESCALE          .equ  2               
FIQ_TICKS_PER_SEC           .equ  100

; Calculate timer count value based on timer clock, timer pre-scale and the number
; of timer ticks per second (100 = 10 ms timer interrupt)
; The equation for this count value is:  count = (CLOCK/PRESCALE) * .010 seconds 

FIQ_TIMER_COUNT             .equ  (FIQ_TIMER_CLOCK/FIQ_TIMER_PRESCALE) / FIQ_TICKS_PER_SEC

FIQ_TIMER_LOAD_VAL          .word FIQ_TIMER_COUNT   ; 32-bit count 
FIQ_TIMER_RESET             .equ  0x00000000

; Timer 1 interrupt bits 
FIQ_TIMER_IRQ               .equ  26
FIQ_TIMER_MASK              .equ  0x04000000
FIQ_TIMER_ILR               .equ  0x0001 

;******************************
;* NUCLEUS TIMER CONSTANTS    *
;******************************
; Page 6-5,6 of the OMAP Dual Core Processor Technical Reference Manual
; Based off TIMER 2
CNTL_TIMER_BASE             .word 0xFFFEC600        ; Define base for all timer registers
LOAD_TIM_OFFSET             .equ  0x04              ; Offset of timer load register from base
TIMER_ENABLE                .equ  0x20              ; Must set this before a timer 
                                                    ; is used (pg 6-5)
TIMER_PTV                   .equ  0x00000000        ; Prescale clock by 2
TIMER_ST                    .equ  0x00000001        ; Bit 0 to start timer
TIMER_AR                    .equ  0x00000002        ; Bit 1 to auto-reload
TIMER_CLOCK                 .equ  84000000          ; Clock used by timer
TIMER_PRESCALE              .equ  2
TIMER_TICKS_PER_SEC         .equ  100

; Calculate timer count value based on timer clock, timer pre-scale and the number
; of timer ticks per second (100 = 10 ms timer interrupt)
; The equation for this count value is:  count = (CLOCK/PRESCALE) * .010 seconds 

TIMER_COUNT                 .equ  (TIMER_CLOCK/TIMER_PRESCALE) / TIMER_TICKS_PER_SEC

TIMER_LOAD_VAL              .word TIMER_COUNT       ; 32-bit count
TIMER_RESET                 .equ  0x00000000

; Timer interrupt bits
TIMER_IRQ                   .equ  30
TIMER_MASK                  .equ  0x40000000
TIMER_ILR                   .equ  0x0000 

MPU_CLK_RESET_CNTL_BASE     .word   0xFFFECE00      ; Base address for MPU Clock/Reset/Power 
                                                    ; Mode Control Register
MPU_IDLECT2_OFFSET          .equ    0x08            ; MPU Idle Mode Entry Register
ENABLE_TIMER_CLK            .equ    0x80            ; Enables clock of MPU timer connected to TIPB

DPLL_CNTL_BASE              .word   0xFFFECF00      ; Base address for MPU Clock Control Register
DPLL_ENABLE_MASK            .equ    0x0010          ; Mask out PLL ENABLE bit 
DPLL_CLOCK_MULT             .word   0x0390          ; DPLL Mult Value (7*12MHz)=84MHz = TIMER_CLOCK

     
;******************************
;* MONITOR CONSTANTS          *
;******************************
; Traffic Controller Registers
EMIFS_CS0_CONFIG             .word 0xFFFECC10
EMIFS_CS1_CONFIG             .word 0xFFFECC14
EMIFS_CS2_CONFIG             .word 0xFFFECC18
EMIFS_CS3_CONFIG             .word 0xFFFECC1C
EMIFF_SDRAM_CONFIG           .word 0xFFFECC20
EMIFF_MRS                    .word 0xFFFECC24

CS0_VALUE                    .word 0x00203339
CS1_VALUE                    .word 0x1139
CS2_VALUE                    .word 0x1139
CS3_VALUE                    .word 0x1139
SDRAM_VALUE                  .word 0x0000BCF4
MRS_VALUE                    .word 0x00000027

WDOG_TIMER_MODE              .word 0xFFFEC808
WDOG_DISABLE_F5              .word 0x00F5
WDOG_DISABLE_A0              .word 0x00A0

;********************************************
;*  TC_TCB and TC_HCB STRUCT OFFSET DEFINES *
;********************************************
TC_CREATED              .equ     0000h          ; Node for linking to created task list
TC_ID                   .equ     000Ch          ; Internal TCB ID
TC_NAME                 .equ     0010h          ; Task name
TC_STATUS               .equ     0018h          ; Task status
TC_DELAYED_SUSPEND      .equ     0019h          ; Delayed task suspension
TC_PRIORITY             .equ     001Ah          ; Task priority
TC_PREEMPTION           .equ     001Bh          ; Task preemption enable
TC_SCHEDULED            .equ     001Ch          ; Task scheduled count
TC_CUR_TIME_SLICE       .equ     0020h          ; Current time slice
TC_STACK_START          .equ     0024h          ; Stack starting address
TC_STACK_END            .equ     0028h          ; Stack ending address
TC_STACK_POINTER        .equ     002Ch          ; Task stack pointer
TC_STACK_SIZE           .equ     0030h          ; Task stack's size
TC_STACK_MINIMUM        .equ     0034h          ; Minimum stack size
TC_CURRENT_PROTECT      .equ     0038h          ; Current protection
TC_SAVED_STACK_PTR      .equ     003Ch          ; Previous stack pointer
TC_ACTIVE_NEXT          .equ     003Ch          ; Next activated HISR
TC_TIME_SLICE           .equ     0040h          ; Task time slice value
TC_ACTIVATION_COUNT     .equ     0040h          ; Activation counter
TC_HISR_ENTRY           .equ     0044h          ; HISR entry function
TC_HISR_SU_MODE         .equ     0058h          ; Sup/User mode indicator for HISRs
TC_HISR_MODULE          .equ     005Ch          ; Module identifier for HISR's
TC_SU_MODE              .equ     00A8h          ; Sup/User mode indicator for Tasks
TC_MODULE               .equ     00ACh          ; Module identifier for Tasks 

; End of low-level initialization constants.

; /******** END ASM_DEFS.ASH ********/