/***************************************************************************** 
*  modified by Louis Beaudoin for uIP-AVR port - November 16, 2003
*  www.embedded-creations.com
*
*  Removed: The debugging calls to the Procyon AVRLIB UART functions and the
*             register dump function was removed
*
*  Modified:
*          The ax88796Write and Read functions/macros were changed to support
*            three methods of communcating with the NIC
*          Interfacing with the AVR ports changed from sbi/cbi/etc functions
*            to direct port names
*****************************************************************************/

//*****************************************************************************
//
// File Name	: 'ax88796.h'
// Title		: ASIX 88796 L Ethernet Interface Driver
// Author		: Pascal Stang
// Created		: 10/22/2002
// Revised		: 10/26/2002
// Version		: 0.1
// Target MCU	: Atmel AVR series
// Editor Tabs	: 4
//
// Description	: This include file is designed to contain items useful to all
//					code files and projects.
//
// Based in part on code by Louis Beaudoin (www.embedded-creations.com)
//
// This code is distributed under the GNU Public License
//		which can be found at http://www.gnu.org/licenses/gpl.txt
//
//*****************************************************************************

#ifndef AX88796_H
#define AX88796_H

#include "delay.h"
#include "compiler.h"
#include "uipopt.h"

#define u08 unsigned char

/*****************************************************************************
*
*  AVR hardware setup
*
*    External SRAM Interfaces:
*    -------------------------------------------------------------------------
*    NIC_CONNECTION == MEMORY_MAPPED
*      The NIC is mapped into memory at the OFFSET location.  The five NIC
*        address lines are taken from the externally latched signals A0-A4.
*        
*    NIC_CONNECTION == MEMORY_MAPPED_HIGHADDR
*      The five NIC address lines are taken from A8-A12 (uses the
*        non-multiplexed address port so no latch is required).  The OFFSET is
*        added to this value, so for example, you can use an offset of 0x8000 
*        and use the A15 pin as a chip select signal
*
*    General I/O Interface:
*    -------------------------------------------------------------------------
*    NIC_CONNECTION == GENERAL_IO
*      One full port is required for the data, and the first five pins from
*        another port is required for address.  The read and write pins can
*        come from another port, or be held in two of the remaining three
*        pins on the address port
*
*    One output pin is required for hard resetting the NIC (In the General I/O
*      this can be from the same port as the address and/or read/write pins)
*
*****************************************************************************/
#define GENERAL_IO 0
#define MEMORY_MAPPED_HIGHADDR 1
#define MEMORY_MAPPED 2

// set the connection type used to communicate with the NIC
#define NIC_CONNECTION GENERAL_IO

#if NIC_CONNECTION != GENERAL_IO
/*** NIC Interface through External SRAM Interface ****/
#define MEMORY_MAPPED_AX88796_OFFSET 0x8000
#else
/************ NIC Interface through General I/O *******************/
// AX88796 address port
#define AX88796_ADDRESS_PORT        PORTC
#define AX88796_ADDRESS_DDR         DDRC
#define AX88796_ADDRESS_MASK		0x1F

// AX88796 data port
#define AX88796_DATA_PORT           PORTA
#define AX88796_DATA_DDR            DDRA
#define AX88796_DATA_PIN            PINA

// AX88796 control port
#define AX88796_CONTROL_PORT        PORTC
#define AX88796_CONTROL_DDR         DDRC
#define AX88796_CONTROL_READPIN     5
#define AX88796_CONTROL_WRITEPIN    6

#endif /** NIC Interface **/

// AX88796 RESET pin
#define AX88796_RESET_PORT 	PORTD
#define AX88796_RESET_DDR 	DDRD
#define AX88796_RESET_PIN 	2



/*****************************************************************************
*
* MAC address for this interface
*
*****************************************************************************/
#define MYMAC_0 UIP_ETHADDR0
#define MYMAC_1 UIP_ETHADDR1
#define MYMAC_2 UIP_ETHADDR2
#define MYMAC_3 UIP_ETHADDR3
#define MYMAC_4 UIP_ETHADDR4
#define MYMAC_5 UIP_ETHADDR5


/*****************************************************************************
*
*  Ethernet constants
*
*****************************************************************************/
#define ETHERNET_MIN_PACKET_LENGTH	0x3C
#define ETHERNET_HEADER_LENGTH		0x0E

//******************************************************************
//*	ASIX 88796 L CONTROL REGISTER OFFSETS
//******************************************************************
// Page 0
#define CR		 	0x00
#define PSTART		0x01
#define PSTOP		0x02
#define BNRY		0x03
#define TSR			0x04
#define TPSR		0x04
#define TBCR0		0x05
#define NCR			0x05
#define TBCR1		0x06
#define ISR			0x07
#define RSAR0		0x08
#define CRDA0		0x08
#define RSAR1		0x09
#define CRDAL		0x09
#define RBCR0		0x0A
#define RBCR1		0x0B
#define RSR			0x0C
#define RCR			0x0C
#define TCR			0x0D
#define CNTR0		0x0D
#define DCR			0x0E
#define CNTR1		0x0E
#define IMR			0x0F
#define CNTR2		0x0F
#define RDMAPORT  	0x10
#define MEMR		0x14
#define TR			0x15
#define GPOC		0x17
#define GPI			0x17
#define SPP_DPR    	0x18
#define SSP_SPR		0x19
#define SSP_CPR		0x1A
#define RSTPORT		0x1F
// Page 1
#define PAR0      	0x01	// Page 1
#define PAR1      	0x02	// Page 1
#define PAR2      	0x03	// Page 1
#define PAR3      	0x04	// Page 1
#define PAR4      	0x05	// Page 1
#define PAR5      	0x06	// Page 1
#define CURR		0x07	// Page 1
#define CPR			0x07	// Page 1

//******************************************************************
//*	ASIX 88796 L CR REGISTER BIT DEFINITIONS
//******************************************************************
#define  PS1		0x80 
#define  PS0		0x40 
#define  RD2		0x20 
#define  RD1		0x10 
#define  RD0		0x08 
#define  TXP		0x04 
#define  START		0x02 
#define  STOP		0x01 
//******************************************************************
//*	ASIX 88796 L RCR REGISTER BIT DEFINITIONS
//******************************************************************
#define  INTT		0x40 
#define  MON		0x20 
#define  PRO		0x10 
#define  AM			0x08 
#define  AB			0x04 
#define  AR			0x02 
#define  SEP		0x01 
//******************************************************************
//*	ASIX 88796 L ISR REGISTER BIT DEFINITIONS
//******************************************************************
#define  RST		0x80
#define  RDC		0x40
#define  OVW		0x10
#define  RXE		0x08
#define  TXE		0x04
#define  PTX		0x02
#define  PRX		0x01
//******************************************************************
//*	ASIX 88796 L TEST REGISTER DEFINITIONS
//******************************************************************
#define  AUTOD		0x01 
#define  RST_B		0x02
#define  RST_10B	0x04
#define  RST_TXB	0x08
//******************************************************************
//*	ASIX 88796 L GPOC BITS DEFINITIONS
//******************************************************************
#define  GPO0		0x01
#define	 MPSEL		0x10
#define  MPSET		0x20
#define  PPDSET		0x40
//******************************************************************
//*	ASIX 88796 L MEMR BITS DEFINITIONS
//******************************************************************
#define  MDC		0x01
#define  MDIR		0x02
#define  MDI		0x04
#define  MDO		0x08
#define  EECS		0x10
#define  EEI		0x20
#define  EEO		0x40