/* FFMC-16 IO-MAP HEADER FILE                                                */
/* ==========================                                                */
/* SOFTUNE WORKBENCH FORMAT                                                  */
/* C-DEFINITIONS FOR IO-SYMBOLS                                              */
/* CREATED BY IO-WIZARD V2.16                                                */
/* $Id: mb90340.h,v 4.8 2004/03/26 12:34:25 dfisch Exp $ */
/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */
/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
/* ELIGIBILITY FOR ANY PURPOSES.                                             */
/*                 (C) Fujitsu Microelectronics Europe GmbH                  */
/* ***************************************************************************** */
/*               FUJITSU MIKROELEKTRONIK GMBH                                */
/*               Am Siebenstein 6-10, 63303 Dreieich                         */
/*               Tel.:++49/6103/690-0,Fax - 122                              */
/*                                                                           */
/* The following software is for demonstration purposes only.                */
/* It is not fully tested, nor validated in order to fullfill                */
/* its task under all circumstances. Therefore, this software                */
/* or any part of it must only be used in an evaluation                      */
/* laboratory environment.                                                   */
/* This software is subject to the rules of our standard                     */
/* DISCLAIMER, that is delivered with our SW-tools (on the CD                */
/* "Micros Documentation & Software V3.0" see "\START.HTM" or                */
/* see our Internet Page -                                                   */
/* http://www.fujitsu-ede.com/products/micro/disclaimer.html                 */
/* ***************************************************************************** */
/*                                                                           */
/* NOTE:                                                                     */
/*                                                                           */
/* This header-file will cover all features of the Emulation chip MB90V340/S. */
/* No Flash- or Mask- version of the MB90340series will support all features !!! */
/* Limitaions can be found in UARTs, CANs, I2C, ADC, etc.                    */
/* Please DO NOT USE resources / registers others than specified             */
/* for the dedicated Flash-/Mask-version.                                    */
/* Please refer to the datasheet and hardwaremanual of the MB90340series.    */
/*                                                                           */
/*                                                                           */
/* ----------------------------------------------------------------------    */
/* Id: mb90340.iow,v 4.6 2004/03/26 08:47:20 dfisch Exp                      */
/* ----------------------------------------------------------------------    */
/* History:                                                                  */
/* Date		Version	Author	Description                                          */
/* 22.10.2002 	1.0 	HWE     created (from MB90390.iow)                       */
/*                              check Register: ICS,ICE,ADC,CDMR, CANSWR     */
/* 27.01.2003   1.1     HWE     PPGCD is double-defined                      */
/*                              Clock-Select-Register are renamed            */
/*                                 PPG01   .. PPGCD  , PPGEF                 */
/*                              => PPGCS01 .. PPGCSCD, PPGCSEF               */
/*                              CDMR: Bit DIRECT added                       */
/*                              CANSWR: Bits TXS01, RXS01 added              */
/*                              ADC_01_new.h corrected                       */
/*                              PRLxy Longwordaccess                         */
/* 03.02.2003   1.2     HWE     Register DCSR: Bitdefinition corrected       */
/*                              Register LPMCR: Bitdefinitions deleted       */
/*                              Register PLLDIV renamed to PSCCR             */
/* 11.02.2003   1.3     DFi     Register DCSR: Groupdefinition DCSR removed  */
/*                             	LPMCR definition only, no declaration        */
/*                              (Standby Cancel Failure)                     */
/* Id: mb90340.iow,v 4.0 2003/05/07 15:10:33 dfisch Exp                      */
/*      - CVS and make controlled                                            */
/* Id: mb90340.iow,v 4.1 2003/08/18 13:50:29 dfisch Exp                      */
/*      - Register ILSR: Bitdefinition corrected,                            */
/*      - Register ILSR: Word splitted: (ILSR0, ILSR1)                       */
/*      - Register DDRA: Bitdefinition updated                               */
/*      - Register DCT, DCTL, DCTH, IOA, IOAL, IOAH, DMACS: Bitdefinition updated */
/*      - Register CMCR: Bitdefinition corrected                             */
/*      - Register WDTC: Bitdefinition WT0, WT1, WTE deleted (Write-only)    */
/*      - Register ARSR, HACR, ECSR: Bitdefinitions deleted (Write-only)     */
/*      - Register TCCS0, TCCS1: Bytedefinition added: TCCSL0, TCCSH0, TCCSL1, TCCSH1 */
/*      - Register WTC: Bits WTC0..2 grouped                                 */
/*      - Register PPGCx: Bitname PEx0 renamed to PEx                        */
/*      - Register ESCR0..3: Bits LBL0..LBL1 grouped                         */
/*      - Register BGRx: Bytedefinition renamed: BGR0x => BGRx0 , BGR1x => BGRx1 */
/*        (BGR00, BGR01) (BGR10, BGR11) (BGR20, BGR21) (BGR30, BGR31) (BGR40, BGR41) */
/*      - UART4 removed (SMR4, SCR4, RDR4, TDR4, SSR4, ECCR4, ESCR4, BGR4, BGR40, BGR41) */
/*      - Clock Modulator removed (CMPR, CMPRL, CMPRH)                       */
/*      - DA-Converter removed (DAT0L, DAT1L, DACR0, DACR1)                  */
/* Id: mb90340.iow,v 4.2 2003/08/29 12:22:20 dfisch Exp                      */
/*      - Register DCSR: Groupdefinition DCSR defined again                  */
/* Id: mb90340.iow,v 4.3 2003/09/08 15:08:32 dfisch Exp                      */
/*      - Register PPGCSxy: Bit0 (REV) added                                 */
/* Id: mb90340.iow,v 4.4 2003/09/16 07:01:17 dfisch Exp                      */
/*      - Address of OCCP6 (0x793C) corrected                                */
/* Id: mb90340.iow,v 4.5 2003/09/18 12:49:35 dfisch Exp                      */
/*      - PRLx Wordaccess added                                              */
/* Id: mb90340.iow,v 4.6 2004/03/26 08:47:20 dfisch Exp                      */
/*      - ECCRx-register: Bitdefinition deleted                              */
/*                                                                           */
/* ----------------------------------------------------------------------    */
/* Id: adc_01_new.h,v 2.2 2003/08/19 09:46:21 dfisch Exp                     */
/* ----------------------------------------------------------------------    */
/* DESCRIPTION:  Interrupt Control Register Declaration                      */
/*                                                                           */
/* AUTHOR:       Fujitsu Mikroelektronik GmbH                                */
/*                                                                           */
/* HISTORY:                                                                  */
/* Version 1.0      22.10.2002 : HWe, original version                       */
/* Version 1.1      15.01.2003 : HWe, ADCS0: Bit0 (STBY) deleted             */
/* Id: adc_01_new.h,v 2.0 2003/05/06 09:00:19 dfisch Exp                     */
/*      - CVS and make controlled                                            */
/* Id: adc_01_new.h,v 2.1 2003/06/27 14:30:51 dfisch Exp                     */
/*      - adapted to BITFIELD_ORDER_MSB                                      */
/* Id: adc_01_new.h,v 2.2 2003/08/19 09:46:21 dfisch Exp                     */
/*      - ADCS0 Bit-defs as const, only Byte-write                           */
/* ----------------------------------------------------------------------    */
/* Id: ICR.H,v 2.1 2003/06/27 14:30:51 dfisch Exp                            */
/* ----------------------------------------------------------------------    */
/*                                                                           */
/* DESCRIPTION:  Interrupt Control Register Declaration                      */
/*                                                                           */
/* AUTHOR:       Fujitsu Mikroelektronik GmbH                                */
/*                                                                           */
/* HISTORY:                                                                  */
/* Version 1.0      26.01.99:                                                */
/*      - original version                                                   */
/* Version 1.2      11.02.99                                                 */
/*      - "extern" changed to pre-defined macro of IO-Wizard                 */
/*        (__IO_EXTERN), requires IO-Wizard 1.7 or later                     */
/*                                                                           */
/* Version 1.3      17.07.2002  HW  Bitdefinitions as const, no RMV allowed  */
/* Id: ICR.H,v 2.0 2003/05/06 09:03:53 dfisch Exp                            */
/*      - CVS and make controlled                                            */
/* Id: ICR.H,v 2.1 2003/06/27 14:30:51 dfisch Exp                            */
/*      - adapted to BITFIELD_ORDER_MSB                                      */
/* ----------------------------------------------------------------------    */
/* Id: CANSTR.H,v 3.1 2003/06/27 14:30:51 dfisch Exp                         */
/* ----------------------------------------------------------------------    */
/* CANIO: control structures of CAN for LX-controllers                       */
/*                                                                           */
/* Version: 1.0            23.01.99     HL                                   */
/*      - original version                                                   */
/* Version: 2.0            26.02.99     HL                                   */
/*      - unsigned int replace by IO_WORD (FR/LX have diff int)              */
/*      - unsigned char replace by IO_BYTE                                   */
/* Version: 2.1            26.08.02     HLo                                  */
/*      - const specifier used for RTEC union                                */
/*      - REC and TEC of RTEC changed from bit group to Byte type            */
/*      - short type addded to DTR register for compatibility                */
/* Id: CANSTR.H,v 3.0 2003/05/06 09:02:30 dfisch Exp                         */
/*      - CVS and make controlled                                            */
/* Id: CANSTR.H,v 3.1 2003/06/27 14:30:51 dfisch Exp                         */
/*      - adapted to BITFIELD_ORDER_MSB                                      */
/* ----------------------------------------------------------------------    */
/* Id: canmac012.h,v 5.0 2003/05/06 09:01:20 dfisch Exp                      */
/* ----------------------------------------------------------------------    */
/* CANIO: control structures for LX-controllers                              */
/*        version 1.0 to 2.2 for double CAN                                  */
/*                                                                           */
/* Version: 1.0            23.01.99     FMG, HLO                             */
/*      - original version                                                   */
/* Version: 1.1            27.01.99     FMG, tka                             */
/*      - idrx0 changed to IDRX0                                             */
/* Version: 1.2            11.02.99     FMG, HLO                             */
/*      - "extern" declaration changed to predefined macros of               */
/*        IO-Wizard, requires IO-Wizard 1.7 or later                         */
/*      - DRT1_LWPTR changed to DTR1_DWPTR macro                             */
/* Version: 2.0            28.05.01     HLO                                  */
/*      - LX-version adopted to FR                                           */
/*      - __IO_EXTENDED changed to __IO_EXTERN, CAN is on external bus       */
/* Version: 2.1            08.06.01     HLO                                  */
/*      - macro for short type in DTR added                                  */
/* Version: 2.2            11.06.01     MEN                                  */
/*      - DLC changed to IO_WORD                                             */
/* Version: 3.0            05.08.02     DF                                   */
/*      - removed CAN1                                                       */
/* Version: 3.1            23.08.02     DF                                   */
/*      - DTR_LWPTR and DTR_DWPTR for compatibility                          */
/* Version: 4.0            23.08.02     HLO                                  */
/*      - changed to batch generation                                        */
/* Id: canmac012.h,v 5.0 2003/05/06 09:01:20 dfisch Exp                      */
/*      - CVS and make controlled                                            */
/* ----------------------------------------------------------------------    */
/* Id: security.asm,v 1.1 2003/08/19 10:25:24 dfisch Exp                     */
/* ----------------------------------------------------------------------    */
/* Id: security.asm,v 1.1 2003/08/19 10:25:24 dfisch Exp                     */
/*      - initial                                                            */


#ifndef   __MB90XXX_H
#  define __MB90XXX_H
/*
- Please define __IO_NEAR in LARGE and COMPACT memory model, if the default
  data bank (DTB) is 00. This will result in better performance in these
  models.
- Please define __IO_FAR in SMALL and MEDIUM memory model, if the default
  data bank (DTB) is other than 00. This might be the case in systems with
  external RAM, which are not using internal RAM as default data area.
- Please define neither __IO_NEAR nor __IO_FAR in all other cases. This
  will work with almost all configurations.
*/

#  ifdef  __IO_NEAR
#    ifdef  __IO_FAR
#      error __IO_NEAR and __IO_FAR must not be defined at the same time
#    else
#      define ___IOWIDTH __near
#    endif
#  else
#    ifdef __IO_FAR
#      define ___IOWIDTH __far
#    else                               /* specified by memory model */
#      define ___IOWIDTH
#    endif
#  endif
#  ifdef  __IO_DEFINE
#    define __IO_EXTERN
#    define __IO_EXTENDED volatile ___IOWIDTH
#  else
#    define __IO_EXTERN   extern      /* for data, which can have __io */
#    define __IO_EXTENDED extern volatile ___IOWIDTH
#  endif

typedef unsigned char		IO_BYTE;
typedef unsigned short		IO_WORD;
typedef unsigned long		IO_LWORD;
typedef const unsigned short	IO_WORD_READ;

/* REGISTER BIT STRUCTURES */

typedef union{   /*  PORT DATA */
    IO_BYTE	byte;
    struct{
    IO_BYTE _P00 :1;
    IO_BYTE _P01 :1;
    IO_BYTE _P02 :1;
    IO_BYTE _P03 :1;
    IO_BYTE _P04 :1;
    IO_BYTE _P05 :1;
    IO_BYTE _P06 :1;
    IO_BYTE _P07 :1;
  }bit;
 }PDR0STR;
typedef union{  
    IO_BYTE	byte;
    struct{
    IO_BYTE _P10 :1;
    IO_BYTE _P11 :1;
    IO_BYTE _P12 :1;
    IO_BYTE _P13 :1;
    IO_BYTE _P14 :1;
    IO_BYTE _P15 :1;
    IO_BYTE _P16 :1;
    IO_BYTE _P17 :1;
  }bit;
 }PDR1STR;
typedef union{  
    IO_BYTE	byte;
    struct{
    IO_BYTE _P20 :1;
    IO_BYTE _P21 :1;
    IO_BYTE _P22 :1;
    IO_BYTE _P23 :1;
    IO_BYTE _P24 :1;
    IO_BYTE _P25 :1;
    IO_BYTE _P26 :1;
    IO_BYTE _P27 :1;
  }bit;
 }PDR2STR;
typedef union{  
    IO_BYTE	byte;
    struct{
    IO_BYTE _P30 :1;
    IO_BYTE _P31 :1;
    IO_BYTE _P32 :1;
    IO_BYTE _P33 :1;
    IO_BYTE _P34 :1;
    IO_BYTE _P35 :1;
    IO_BYTE _P36 :1;
    IO_BYTE _P37 :1;
  }bit;
 }PDR3STR;
typedef union{  
    IO_BYTE	byte;
    struct{
    IO_BYTE _P40 :1;
    IO_BYTE _P41 :1;
    IO_BYTE _P42 :1;
    IO_BYTE _P43 :1;
    IO_BYTE _P44 :1;
    IO_BYTE _P45 :1;
    IO_BYTE _P46 :1;
    IO_BYTE _P47 :1;
  }bit;
 }PDR4STR;
typedef union{  
    IO_BYTE	byte;
    struct{
    IO_BYTE _P50 :1;
    IO_BYTE _P51 :1;
    IO_BYTE _P52 :1;
    IO_BYTE _P53 :1;
    IO_BYTE _P54 :1;
    IO_BYTE _P55 :1;
    IO_BYTE _P56 :1;
    IO_BYTE _P57 :1;
  }bit;
 }PDR5STR;
typedef union{  
    IO_BYTE	byte;
    struct{
    IO_BYTE _P60 :1;
    IO_BYTE _P61 :1;
    IO_BYTE _P62 :1;
    IO_BYTE _P63 :1;
    IO_BYTE _P64 :1;
    IO_BYTE _P65 :1;
    IO_BYTE _P66 :1;
    IO_BYTE _P67 :1;
  }bit;
 }PDR6STR;
typedef union{  
    IO_BYTE	byte;
    struct{
    IO_BYTE _P70 :1;
    IO_BYTE _P71 :1;
    IO_BYTE _P72 :1;
    IO_BYTE _P73 :1;
    IO_BYTE _P74 :1;
    IO_BYTE _P75 :1;
    IO_BYTE _P76 :1;
    IO_BYTE _P77 :1;
  }bit;
 }PDR7STR;
typedef union{  
    IO_BYTE	byte;
    struct{
    IO_BYTE _P80 :1;
    IO_BYTE _P81 :1;
    IO_BYTE _P82 :1;
    IO_BYTE _P83 :1;
    IO_BYTE _P84 :1;
    IO_BYTE _P85 :1;
    IO_BYTE _P86 :1;
    IO_BYTE _P87 :1;
  }bit;
 }PDR8STR;
typedef union{  
    IO_BYTE	byte;
    struct{
    IO_BYTE _P90 :1;
    IO_BYTE _P91 :1;
    IO_BYTE _P92 :1;
    IO_BYTE _P93 :1;
    IO_BYTE _P94 :1;
    IO_BYTE _P95 :1;
    IO_BYTE _P96 :1;
    IO_BYTE _P97 :1;
  }bit;
 }PDR9STR;
typedef union{  
    IO_BYTE	byte;
    struct{
    IO_BYTE _PA0 :1;
    IO_BYTE _PA1 :1;
    IO_BYTE  :1;
    IO_BYTE  :1;
    IO_BYTE  :1;
    IO_BYTE  :1;
    IO_BYTE  :1;
    IO_BYTE  :1;
  }bit;
 }PDRASTR;
typedef union{  
    IO_BYTE	byte;
    struct{
    IO_BYTE _ADE8 :1;
    IO_BYTE _ADE9 :1;
    IO_BYTE _ADE10 :1;
    IO_BYTE _ADE11 :1;
    IO_BYTE _ADE12 :1;
    IO_BYTE _ADE13 :1;
    IO_BYTE _ADE14 :1;
    IO_BYTE _ADE15 :1;
  }bit;
 }ADER5STR;
typedef union{  
    IO_BYTE	byte;
    struct{
    IO_BYTE _ADE0 :1;
    IO_BYTE _ADE1 :1;
    IO_BYTE _ADE2 :1;
    IO_BYTE _ADE3 :1;
    IO_BYTE _ADE4 :1;
    IO_BYTE _ADE5 :1;
    IO_BYTE _ADE6 :1;
    IO_BYTE _ADE7 :1;
  }bit;
 }ADER6STR;
typedef union{  
    IO_BYTE	byte;
    struct{
    IO_BYTE _ADE16 :1;
    IO_BYTE _ADE17 :1;
    IO_BYTE _ADE18 :1;
    IO_BYTE _ADE19 :1;
    IO_BYTE _ADE20 :1;
    IO_BYTE _ADE21 :1;
    IO_BYTE _ADE22 :1;
    IO_BYTE _ADE23 :1;
  }bit;
 }ADER7STR;
typedef union{  
    IO_WORD	word;
    struct{
    IO_WORD _IL0 :1;
    IO_WORD _IL1 :1;
    IO_WORD _IL2 :1;
    IO_WORD _IL3 :1;
    IO_WORD _IL4 :1;
    IO_WORD _IL5 :1;
    IO_WORD _IL6 :1;
    IO_WORD _IL7 :1;
    IO_WORD _IL8 :1;
    IO_WORD _IL9 :1;
    IO_WORD _ILA :1;
    IO_WORD  :1;
    IO_WORD _ILT0 :1;
    IO_WORD _ILT1 :1;
    IO_WORD _ILT2 :1;
    IO_WORD _ILT3 :1;
  }bit;
 }ILSRSTR;
typedef union{  
    IO_BYTE	byte;
    struct{
    IO_BYTE _IL0 :1;
    IO_BYTE _IL1 :1;
    IO_BYTE _IL2 :1;
    IO_BYTE _IL3 :1;
    IO_BYTE _IL4 :1;
    IO_BYTE _IL5 :1;
    IO_BYTE _IL6 :1;
    IO_BYTE _IL7 :1;
  }bit;
 }ILSR0STR;
typedef union{  
    IO_BYTE	byte;
    struct{
    IO_BYTE _IL8 :1;
    IO_BYTE _IL9 :1;
    IO_BYTE _ILA :1;
    IO_BYTE  :1;
    IO_BYTE _ILT0 :1;
    IO_BYTE _ILT1 :1;
    IO_BYTE _ILT2 :1;
    IO_BYTE _ILT3 :1;
  }bit;
 }ILSR1STR;
typedef union{   /*  PORT DIRECTION */
    IO_BYTE	byte;
    struct{
    IO_BYTE _D00 :1;
    IO_BYTE _D01 :1;
    IO_BYTE _D02 :1;
    IO_BYTE _D03 :1;
    IO_BYTE _D04 :1;
    IO_BYTE _D05 :1;
    IO_BYTE _D06 :1;
    IO_BYTE _D07 :1;
  }bit;
 }DDR0STR;
typedef union{  
    IO_BYTE	byte;
    struct{
    IO_BYTE _D10 :1;
    IO_BYTE _D11 :1;
    IO_BYTE _D12 :1;
    IO_BYTE _D13 :1;
    IO_BYTE _D14 :1;
    IO_BYTE _D15 :1;
    IO_BYTE _D16 :1;
    IO_BYTE _D17 :1;
  }bit;
 }DDR1STR;
typedef union{  
    IO_BYTE	byte;
    struct{
    IO_BYTE _D20 :1;
    IO_BYTE _D21 :1;
    IO_BYTE _D22 :1;
    IO_BYTE _D23 :1;
    IO_BYTE _D24 :1;
    IO_BYTE _D25 :1;
    IO_BYTE _D26 :1;
    IO_BYTE _D27 :1;
  }bit;
 }DDR2STR;
typedef union{  
    IO_BYTE	byte;
    struct{
    IO_BYTE _D30 :1;
    IO_BYTE _D31 :1;
    IO_BYTE _D32 :1;
    IO_BYTE _D33 :1;
    IO_BYTE _D34 :1;
    IO_BYTE _D35 :1;
    IO_BYTE _D36 :1;
    IO_BYTE _D37 :1;
  }bit;
 }DDR3STR;
typedef union{  
    IO_BYTE	byte;
    struct{
    IO_BYTE _D40 :1;
    IO_BYTE _D41 :1;
    IO_BYTE _D42 :1;
    IO_BYTE _D43 :1;
    IO_BYTE _D44 :1;
    IO_BYTE _D45 :1;
    IO_BYTE _D46 :1;
    IO_BYTE _D47 :1;
  }bit;
 }DDR4STR;
typedef union{  
    IO_BYTE	byte;
    struct{
    IO_BYTE _D50 :1;
    IO_BYTE _D51 :1;
    IO_BYTE _D52 :1;
    IO_BYTE _D53 :1;
    IO_BYTE _D54 :1;
    IO_BYTE _D55 :1;
    IO_BYTE _D56 :1;
    IO_BYTE _D57 :1;
  }bit;
 }DDR5STR;
typedef union{  
    IO_BYTE	byte;
    struct{
    IO_BYTE _D60 :1;
    IO_BYTE _D61 :1;
    IO_BYTE _D62 :1;
    IO_BYTE _D63 :1;
    IO_BYTE _D64 :1;
    IO_BYTE _D65 :1;
    IO_BYTE _D66 :1;
    IO_BYTE _D67 :1;
  }bit;
 }DDR6STR;
typedef union{  
    IO_BYTE	byte;
    struct{
    IO_BYTE _D70 :1;
    IO_BYTE _D71 :1;
    IO_BYTE _D72 :1;
    IO_BYTE _D73 :1;
    IO_BYTE _D74 :1;
    IO_BYTE _D75 :1;
    IO_BYTE _D76 :1;
    IO_BYTE _D77 :1;
  }bit;
 }DDR7STR;
typedef union{  
    IO_BYTE	byte;
    struct{
    IO_BYTE _D80 :1;
    IO_BYTE _D81 :1;
    IO_BYTE _D82 :1;
    IO_BYTE _D83 :1;
    IO_BYTE _D84 :1;
    IO_BYTE _D85 :1;
    IO_BYTE _D86 :1;
    IO_BYTE _D87 :1;
  }bit;
 }DDR8STR;
typedef union{  
    IO_BYTE	byte;
    struct{
    IO_BYTE _D90 :1;
    IO_BYTE _D91 :1;
    IO_BYTE _D92 :1;