not_w_rdpredec:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	;;  not.w @-eRd	mov	#word_dest+2, er1	not.w	@-er1		; reg pre-decr operand;;;	.word	0x0157;;;	.word	0x6d18;;;	.word	0x1710	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0	test_ovf_clear	test_zero_clear	test_neg_clear	cmp.w	#0x5a5a, @word_dest	beq	.Lwpredec	fail.Lwpredec:	test_h_gr32 word_dest er1	; er1 contains destination address 	test_gr_a5a5 0		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7not_w_disp2dst:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	;;  not.w @(dd:2, erd)	mov	#word_dest-2, er1	not.w	@(2:2, er1)	; reg plus 2-bit displacement;;; 	.word	0x0155;;; 	.word	0x6918;;; 	.word	0x1710	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0	test_ovf_clear	test_zero_clear	test_neg_set	cmp.w	#0xa5a5, @word_dest	beq	.Lwdisp2	fail.Lwdisp2:	test_h_gr32 word_dest-2 er1	; er1 contains address minus one	test_gr_a5a5 0		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7not_w_disp16dst:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	;;  not.w @(dd:16, erd)	mov	#word_dest+100, er1	not.w	@(-100:16, er1)	; reg plus 16-bit displacement;;;	.word	0x0154;;;	.word	0x6f18;;;	.word	-100;;;	.word	0x1710	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0	test_ovf_clear	test_zero_clear	test_neg_clear	cmp.w	#0x5a5a, @word_dest	beq	.Lwdisp16	fail.Lwdisp16:	test_h_gr32 word_dest+100 er1	; er1 contains destination address 	test_gr_a5a5 0		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7not_w_disp32dst:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	;;  not.w @(dd:32, erd)	mov	#word_dest-0xfffff, er1	not.w	@(0xfffff:32, er1)	; reg plus 32-bit displacement;;;	.word	0x7814;;;	.word	0x6b28;;;	.long	0xfffff;;;	.word	0x1710	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0	test_ovf_clear	test_zero_clear	test_neg_set	cmp.w	#0xa5a5, @word_dest	beq	.Lwdisp32	fail.Lwdisp32:	test_h_gr32 word_dest-0xfffff er1 ; er1 contains destination address	test_gr_a5a5 0		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7not_w_abs16dst:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	;;  not.w @aa:16	not.w	@word_dest:16	; 16-bit absolute address;;;	.word	0x6b18;;;	.word	word_dest;;;	.word	0x1710	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0	test_ovf_clear	test_zero_clear	test_neg_clear	cmp.w	#0x5a5a, @word_dest	beq	.Lwabs16	fail.Lwabs16:	test_gr_a5a5 0		; Make sure ALL general regs not disturbed	test_gr_a5a5 1	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7not_w_abs32dst:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	;;  not.w @aa:32	not.w	@word_dest:32	; 32-bit absolute address;;;	.word	0x6b38;;;	.long	word_dest;;;	.word	0x1710	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0	test_ovf_clear	test_zero_clear	test_neg_set	cmp.w	#0xa5a5, @word_dest	beq	.Lwabs32	fail.Lwabs32:	test_gr_a5a5 0		; Make sure ALL general regs not disturbed	test_gr_a5a5 1	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7.endif				; h8sx.endif				; h8/300	#	# 32-bit word operations	#.if (sim_cpu)			; any except plain-vanilla h8/300not_l_reg16:	set_grs_a5a5		; Fill all general regs with a fixed pattern	;;  fixme set ccr	;;  not.l eRd	not	er1		; 32-bit register operand;;;	.word	0x1731	cmp.l	#0x5a5a5a5a, er1	; result of "not 0xa5a5a5a5"	beq	.Llrd	fail.Llrd:		;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0	test_h_gr32 0x5a5a5a5a er1	; er1 changed by 'not' 	test_gr_a5a5 0		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7.if (sim_cpu == h8sx)not_l_rdind:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	;;  not.l @eRd	mov	#long_dest, er1	not.l	@er1		; register indirect operand;;;	.word	0x0104;;;	.word	0x6d18;;;	.word	0x1730	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0	test_ovf_clear	test_zero_clear	test_neg_clear	cmp.l	#0x5a5a5a5a, @long_dest	; memory contents changed	beq	.Llind	fail.Llind:	test_h_gr32 long_dest er1	; er1 still contains address	test_gr_a5a5 0		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7not_l_rdpostinc:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	;;  not.l @eRd+	mov	#long_dest, er1	; register post-increment operand	not.l	@er1+;;;	.word	0x0104;;;	.word	0x6d18;;;	.word	0x1730	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0	test_ovf_clear	test_zero_clear	test_neg_set	cmp.l	#0xa5a5a5a5, @long_dest	beq	.Llpostinc	fail.Llpostinc:	test_h_gr32 long_dest+4 er1	; er1 contains address plus two	test_gr_a5a5 0		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7not_l_rdpostdec:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	;;  not.l @eRd-	mov	#long_dest, er1	not.l	@er1-;;;	.word	0x0106;;;	.word	0x6d18;;;	.word	0x1730	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0	test_ovf_clear	test_zero_clear	test_neg_clear	cmp.l	#0x5a5a5a5a, @long_dest	beq	.Llpostdec	fail.Llpostdec:	test_h_gr32 long_dest-4 er1	; er1 contains address minus two	test_gr_a5a5 0		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7not_l_rdpreinc:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	;;  not.l @+eRd	mov	#long_dest-4, er1	not.l	@+er1		; reg pre-increment operand;;;	.word	0x0105;;;	.word	0x6d18;;;	.word	0x1730	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0	test_ovf_clear	test_zero_clear	test_neg_set	cmp.l	#0xa5a5a5a5, @long_dest	beq	.Llpreinc	fail.Llpreinc:	test_h_gr32 long_dest er1	; er1 contains destination address 	test_gr_a5a5 0		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7not_l_rdpredec:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	;;  not.l @-eRd	mov	#long_dest+4, er1	not.l	@-er1		; reg pre-decr operand;;;	.word	0x0107;;;	.word	0x6d18;;;	.word	0x1730	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0	test_ovf_clear	test_zero_clear	test_neg_clear	cmp.l	#0x5a5a5a5a, @long_dest	beq	.Llpredec	fail.Llpredec:	test_h_gr32 long_dest er1	; er1 contains destination address 	test_gr_a5a5 0		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7not_l_disp2dst:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	;;  not.l @(dd:2, erd)	mov	#long_dest-4, er1	not.l	@(4:2, er1)	; reg plus 2-bit displacement;;; 	.word	0x0105;;; 	.word	0x6918;;; 	.word	0x1730	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0	test_ovf_clear	test_zero_clear	test_neg_set	cmp.l	#0xa5a5a5a5, @long_dest	beq	.Lldisp2	fail.Lldisp2:	test_h_gr32 long_dest-4 er1	; er1 contains address minus one	test_gr_a5a5 0		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7not_l_disp16dst:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	;;  not.l @(dd:16, erd)	mov	#long_dest+100, er1	not.l	@(-100:16, er1)	; reg plus 16-bit displacement;;;	.word	0x0104;;;	.word	0x6f18;;;	.word	-100;;;	.word	0x1730	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0	test_ovf_clear	test_zero_clear	test_neg_clear	cmp.l	#0x5a5a5a5a, @long_dest	beq	.Lldisp16	fail.Lldisp16:	test_h_gr32 long_dest+100 er1	; er1 contains destination address 	test_gr_a5a5 0		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7not_l_disp32dst:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	;;  not.l @(dd:32, erd)	mov	#long_dest-0xfffff, er1	not.l	@(0xfffff:32, er1)	; reg plus 32-bit displacement;;;	.word	0x7894;;;	.word	0x6b28;;;	.long	0xfffff;;;	.word	0x1730	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0	test_ovf_clear	test_zero_clear	test_neg_set	cmp.l	#0xa5a5a5a5, @long_dest	beq	.Lldisp32	fail.Lldisp32:	test_h_gr32 long_dest-0xfffff er1 ; er1 contains destination address	test_gr_a5a5 0		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7not_l_abs16dst:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	;;  not.l @aa:16	not.l	@long_dest:16	; 16-bit absolute address;;;	.word	0x0104;;;	.word	0x6b08;;;	.word	long_dest;;;	.word	0x1730	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0	test_ovf_clear	test_zero_clear	test_neg_clear	cmp.l	#0x5a5a5a5a, @long_dest	beq	.Llabs16	fail.Llabs16:	test_gr_a5a5 0		; Make sure ALL general regs not disturbed	test_gr_a5a5 1	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7not_l_abs32dst:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	;;  not.l @aa:32	not.l	@long_dest:32	; 32-bit absolute address;;;	.word	0x0104;;;	.word	0x6b28;;;	.long	long_dest;;;	.word	0x1730	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0	test_ovf_clear	test_zero_clear	test_neg_set	cmp.l	#0xa5a5a5a5, @long_dest	beq	.Llabs32	fail.Llabs32:	test_gr_a5a5 0		; Make sure ALL general regs not disturbed	test_gr_a5a5 1	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7.endif				; h8sx.endif				; h8/300	pass	exit 0