# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic       
# functions, and any output files any of the foregoing           
# (including device programming or simulation files), and any    
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License      
# Subscription Agreement, Altera MegaCore Function License       
# Agreement, or other applicable license agreement, including,   
# without limitation, that your use is for the sole purpose of   
# programming logic devices manufactured by Altera and sold by   
# Altera or its authorized distributors.  Please refer to the    
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		FFT_32K_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 5.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:49:15  JUNE 20, 2005"
set_global_assignment -name LAST_QUARTUS_VERSION 5.0
set_global_assignment -name VERILOG_FILE ../source/clk_pll.v
set_global_assignment -name VERILOG_FILE ../source/twiddle_rom_add.v
set_global_assignment -name VERILOG_FILE ../source/comb_final_fft_res.v
set_global_assignment -name VERILOG_FILE ../source/combine_fft.v
set_global_assignment -name VERILOG_FILE ../source/fft_32K.v
set_global_assignment -name VERILOG_FILE ../source/fft_small.v
set_global_assignment -name VERILOG_FILE ../source/mram_buf.v
set_global_assignment -name VERILOG_FILE ../source/mul_fft_bot_tf.v
set_global_assignment -name VERILOG_FILE ../source/mult_add.v
set_global_assignment -name VERILOG_FILE ../source/parse_fft_input.v
set_global_assignment -name VERILOG_FILE ../source/scale_fft_res.v
set_global_assignment -name VHDL_FILE "C:/software/altera/MegaCore/fft-v2.1.3/lib/fft_pack.vhd"
set_global_assignment -name VERILOG_FILE "C:/altera/design_example/fft_32K/source/fft_small.v"

# Timing Assignments
# ==================
set_global_assignment -name IGNORE_CLOCK_SETTINGS ON

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE FASTEST
set_global_assignment -name FAMILY "Stratix II"
set_global_assignment -name TOP_LEVEL_ENTITY fft_32K
set_global_assignment -name USER_LIBRARIES "C:/software/altera/MegaCore/fft-v2.1.3/lib;"

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE AUTO
set_global_assignment -name OPTIMIZE_FAST_CORNER_TIMING ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1