?? fft_32k.map.rpt
字號:
Analysis & Synthesis report for FFT_32K
Tue Apr 25 13:20:01 2006
Version 5.0 Build 148 04/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Failed - Tue Apr 25 13:20:01 2006 ;
; Quartus II Version ; 5.0 Build 148 04/26/2005 SJ Full Version ;
; Revision Name ; FFT_32K ;
; Top-level Entity Name ; fft_32K ;
; Family ; Stratix II ;
+-----------------------------+------------------------------------------+
+---------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+--------------------------------------------------------------------+--------------+---------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------+--------------+---------------+
; Top-level entity name ; fft_32K ; FFT_32K ;
; Family name ; Stratix II ; Stratix ;
; Use smart compilation ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; off ; off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; DSP Block Balancing ; Auto ; Auto ;
; Maximum DSP Block Usage ; -1 ; -1 ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- Stratix II ; Balanced ; Balanced ;
; Carry Chain Length -- Stratix II ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Remove Duplicate Logic ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Perform gate-level register retiming ; Off ; Off ;
; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto DSP Block Replacement ; On ; On ;
; Auto Shift Register Replacement ; On ; On ;
; Auto Clock Enable Replacement ; On ; On ;
; Allows Synchronous Control Signal Usage in Normal Mode Logic Cells ; On ; On ;
; Auto RAM Block Balancing ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Maximum Number of M512 Memory Blocks ; -1 ; -1 ;
; Maximum Number of M4K Memory Blocks ; -1 ; -1 ;
; Maximum Number of M-RAM Memory Blocks ; -1 ; -1 ;
; Ignore translate_off and translate_on Synthesis Directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
+--------------------------------------------------------------------+--------------+---------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------+-------------------------------------------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------+-------------------------------------------------------------------------------------------------------------------+
; ../source/clk_pll.v ; yes ; User Verilog HDL File ; C:/Documents and Settings/All Users/Documents/文件/fft_32K/altera/design_example/fft_32K/source/clk_pll.v ;
; ../source/fft_32K.v ; yes ; User Verilog HDL File ; C:/Documents and Settings/All Users/Documents/文件/fft_32K/altera/design_example/fft_32K/source/fft_32K.v ;
; ../source/fft_small.v ; yes ; User Verilog HDL File ; C:/Documents and Settings/All Users/Documents/文件/fft_32K/altera/design_example/fft_32K/source/fft_small.v ;
; ../source/parse_fft_input.v ; yes ; User Verilog HDL File ; C:/Documents and Settings/All Users/Documents/文件/fft_32K/altera/design_example/fft_32K/source/parse_fft_input.v ;
; altpll.tdf ; yes ; Megafunction ; e:/altera/quartus50/libraries/megafunctions/altpll.tdf ;
; aglobal50.inc ; yes ; Other ; e:/altera/quartus50/libraries/megafunctions/aglobal50.inc ;
; stratix_pll.inc ; yes ; Other ; e:/altera/quartus50/libraries/megafunctions/stratix_pll.inc ;
; stratixii_pll.inc ; yes ; Other ; e:/altera/quartus50/libraries/megafunctions/stratixii_pll.inc ;
; cycloneii_pll.inc ; yes ; Other ; e:/altera/quartus50/libraries/megafunctions/cycloneii_pll.inc ;
+----------------------------------+-----------------+------------------------+-------------------------------------------------------------------------------------------------------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Tue Apr 25 13:19:59 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off FFT_32K -c FFT_32K
Info: Found 1 design units, including 1 entities, in source file ../source/clk_pll.v
Info: Found entity 1: clk_pll
Info: Found 1 design units, including 1 entities, in source file ../source/twiddle_rom_add.v
Info: Found entity 1: twiddle_rom_add
Info: Found 1 design units, including 1 entities, in source file ../source/comb_final_fft_res.v
Info: Found entity 1: comb_final_fft_res
Info: Found 1 design units, including 1 entities, in source file ../source/combine_fft.v
Info: Found entity 1: combine_fft
Info: Found 1 design units, including 1 entities, in source file ../source/fft_32K.v
Info: Found entity 1: fft_32K
Info: Found 1 design units, including 1 entities, in source file ../source/fft_small.v
Info: Found entity 1: fft_small
Info: Found 1 design units, including 1 entities, in source file ../source/mram_buf.v
Info: Found entity 1: mram_buf
Info: Found 1 design units, including 1 entities, in source file ../source/mul_fft_bot_tf.v
Info: Found entity 1: mul_fft_bot_tf
Info: Found 1 design units, including 1 entities, in source file ../source/mult_add.v
Info: Found entity 1: mult_add
Info: Found 1 design units, including 1 entities, in source file ../source/parse_fft_input.v
Info: Found entity 1: parse_fft_input
Info: Found 1 design units, including 1 entities, in source file ../source/scale_fft_res.v
Info: Found entity 1: scale_fft_res
Warning: Can't analyze file -- file C:/software/altera/MegaCore/fft-v2.1.3/lib/fft_pack.vhd is missing
Warning: Can't analyze file -- file C:/altera/design_example/fft_32K/source/fft_small.v is missing
Info: Elaborating entity "fft_32K" for the top level hierarchy
Info: Elaborating entity "clk_pll" for hierarchy "clk_pll:clk_pll_inst"
Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus50/libraries/megafunctions/altpll.tdf
Info: Found entity 1: altpll
Info: Elaborating entity "altpll" for hierarchy "clk_pll:clk_pll_inst|altpll:altpll_component"
Info: Elaborating entity "parse_fft_input" for hierarchy "parse_fft_input:parse_fft_input_inst"
Warning: Verilog HDL assignment warning at parse_fft_input.v(105): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at parse_fft_input.v(138): truncated value with size 32 to match size of target (16)
Warning: Verilog HDL assignment warning at parse_fft_input.v(139): truncated value with size 32 to match size of target (16)
Warning: Verilog HDL assignment warning at parse_fft_input.v(140): truncated value with size 32 to match size of target (16)
Warning: Verilog HDL assignment warning at parse_fft_input.v(141): truncated value with size 32 to match size of target (16)
Warning: Verilog HDL assignment warning at parse_fft_input.v(142): truncated value with size 32 to match size of target (16)
Warning: Verilog HDL assignment warning at parse_fft_input.v(143): truncated value with size 32 to match size of target (16)
Warning: Verilog HDL assignment warning at parse_fft_input.v(162): truncated value with size 32 to match size of target (16)
Warning: Verilog HDL assignment warning at parse_fft_input.v(163): truncated value with size 32 to match size of target (16)
Warning: Verilog HDL assignment warning at parse_fft_input.v(164): truncated value with size 32 to match size of target (16)
Warning: Verilog HDL assignment warning at parse_fft_input.v(165): truncated value with size 32 to match size of target (16)
Warning: Verilog HDL assignment warning at parse_fft_input.v(166): truncated value with size 32 to match size of target (16)
Warning: Verilog HDL assignment warning at parse_fft_input.v(167): truncated value with size 32 to match size of target (16)
Info: Elaborating entity "fft_small" for hierarchy "fft_small:fft_small_top"
Error: Node instance "asj_fft_dualstream_inst" instantiates undefined entity "asj_fft_dualstream"
Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 15 warnings
Error: Processing ended: Tue Apr 25 13:20:01 2006
Error: Elapsed time: 00:00:03
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -