library verilog;use verilog.vl_types.all;entity obuft_lvcmos15_s_8 is    generic(        cds_action      : string  := "ignore"    );    port(        o               : out    vl_logic;        i               : in     vl_logic;        t               : in     vl_logic    );end obuft_lvcmos15_s_8;