library verilog;use verilog.vl_types.all;entity ilflxi_1f is    generic(        cds_action      : string  := "ignore";        init            : integer := 1    );    port(        q               : out    vl_logic;        d               : in     vl_logic;        g               : in     vl_logic;        ge              : in     vl_logic;        gf              : in     vl_logic    );end ilflxi_1f;