library verilog;use verilog.vl_types.all;entity ram16x1d is    generic(        cds_action      : string  := "ignore";        init            : integer := 0    );    port(        dpo             : out    vl_logic;        spo             : out    vl_logic;        a0              : in     vl_logic;        a1              : in     vl_logic;        a2              : in     vl_logic;        a3              : in     vl_logic;        d               : in     vl_logic;        dpra0           : in     vl_logic;        dpra1           : in     vl_logic;        dpra2           : in     vl_logic;        dpra3           : in     vl_logic;        wclk            : in     vl_logic;        we              : in     vl_logic    );end ram16x1d;