library verilog;use verilog.vl_types.all;entity lut3_d is    generic(        init            : integer := 0    );    port(        lo              : out    vl_logic;        o               : out    vl_logic;        i0              : in     vl_logic;        i1              : in     vl_logic;        i2              : in     vl_logic    );end lut3_d;