library verilog;use verilog.vl_types.all;entity ofddrtrse is    port(        o               : out    vl_logic;        c0              : in     vl_logic;        c1              : in     vl_logic;        ce              : in     vl_logic;        d0              : in     vl_logic;        d1              : in     vl_logic;        r               : in     vl_logic;        s               : in     vl_logic;        t               : in     vl_logic    );end ofddrtrse;