library verilog;use verilog.vl_types.all;entity srl16e_1 is    generic(        cds_action      : string  := "ignore";        init            : integer := 0    );    port(        q               : out    vl_logic;        a0              : in     vl_logic;        a1              : in     vl_logic;        a2              : in     vl_logic;        a3              : in     vl_logic;        ce              : in     vl_logic;        clk             : in     vl_logic;        d               : in     vl_logic    );end srl16e_1;