library verilog;use verilog.vl_types.all;entity mult18x18s is    port(        p               : out    vl_logic_vector(35 downto 0);        a               : in     vl_logic_vector(17 downto 0);        b               : in     vl_logic_vector(17 downto 0);        c               : in     vl_logic;        ce              : in     vl_logic;        r               : in     vl_logic    );end mult18x18s;