library verilog;use verilog.vl_types.all;entity saddcevht is    generic(        create_rpm      : integer := 0;        port_width      : integer := 8    );    port(        a               : in     vl_logic_vector;        b               : in     vl_logic_vector;        c               : in     vl_logic;        ce              : in     vl_logic;        clrci           : in     vl_logic;        sd              : out    vl_logic_vector    );end saddcevht;