library verilog;use verilog.vl_types.all;entity addsvht is    generic(        input_width     : integer := 8;        output_width    : integer := 10    );    port(        a               : in     vl_logic_vector;        b               : in     vl_logic_vector;        ce              : in     vl_logic;        c               : in     vl_logic;        ci              : in     vl_logic;        s               : out    vl_logic_vector    );end addsvht;