library verilog;use verilog.vl_types.all;entity kcmpipevht is    generic(        a_width         : integer := 15;        coefficient     : integer := 2;        coef_width      : integer := 3;        signed_coefficient: integer := 1;        signed_input_data: integer := 1;        registered      : integer := 1    );    port(        a               : in     vl_logic_vector;        c               : in     vl_logic;        prod            : out    vl_logic_vector    );end kcmpipevht;