/******************************************************************//* timer.h - v0.00                                                *//* Copyright (c) 1997 Texas Instruments Incorporated              *//******************************************************************//******************************************************************//* Define Timer Period, and Control Registers with all related    *//* data structures, macros, and functions                         *//******************************************************************/#include "regs54xx.h"
/******************************************************************//* TIMER_START - starts timer operation                           *//******************************************************************/#define TIMER_START(port)\        TCR(port) &= ~MASK_BIT(TSS)/******************************************************************//* TIMER_HALT - halts timer operation                             *//******************************************************************/#define TIMER_HALT(port)\        TCR(port) |= MASK_BIT(TSS)/******************************************************************//* TCR_MASK - creates mask to set relevant fields in Timer Cntrl  *//*           register                                             *//*   trb    - val to set timer reload bit                         *//*   tss    - val to set timer stop/start bit                     *//*   tddr   - val to set timer divide-down ratio                  *//******************************************************************/#define TCR_MASK(trb, tss, tddr)\         ((trb ? MASK_BIT(TRB) | MASK_TARGET_WORD: ~MASK_BIT(TRB))&\          (tss ? MASK_BIT(TSS) | MASK_TARGET_WORD: ~MASK_BIT(TSS))&\          (tddr ? (MASK_FIELD(TDDR,tddr, TDDR_SZ) | MASK_TARGET_WORD) :\                 ~MASK_FIELD(TDDR,tddr, TDDR_SZ))) /******************************************************************//* TIMER_INIT (ctrl, prd) - init and start timer                  *//*  ctrl - mask used to set timer control register                *//*  prd  - value to set timer period register                     *//*****(************************************************************/#define TIMER_INIT(port, ctrl, prd)\       { SET_BIT(TCR_ADDR(port),TSS);\         TCR(port) = ctrl;\         PRD(port) = prd;\         TIMER_RELOAD(port); }/******************************************************************//* timer_reset - reset timer to conditions defined by device reset*//*  i.e.  period = 0xffff    , tddr = 0x000                       *//******************************************************************/#define TIMER_RESET(port)\	{ TIMER_HALT(port);\          LOAD_FIELD(TCR_ADDR(port), 0x000, TDDR, TDDR_SZ);\          PRD(port) = 0xffff;\          TIMER_START(port); }/******************************************************************//* TIMER_RELOAD() - reloads timer with previsouly set             *//*                  period value, etc..                           *//******************************************************************/#define TIMER_RELOAD(port)\	{ TIMER_HALT(port);\	  TCR(port) |= MASK_BIT(TRB);\          TIMER_START(port); }/******************************************************************//* TIMER_READ - reads current value of timer                      *//******************************************************************/#define TIMER_READ(port)\	TIM(port)/******************************************************************//* MASK_CLKMD(PLLMUL, PLLDIV, PLLCOUNT, PLLONOFF, PLLNDIV)        *//*           creates mas kto set PLL clock mode register          *//*                                                                *//* PLLMUL - defines frequency multiplier                          *//* PLLDIV - PLL divider is used with PLLMUL & PLLNDIV to          *//*          define multiplier frequency                           *//*                                                                *//* PLLCOUNT - # of cycles for PLL to count before processor       *//*            is clocked                                          *//*                                                                *//* PLLONOFF - enables/disables the analog part of the PLL         *//* PLLNDIV  - in conjunction with PLLMIL & PLLDIV determines      *//*            value of multiplier.                                *//******************************************************************/#define MASK_CLKMD(pllmul, plldiv, pllcount, pllonoff, pllndiv)\      ((pllmul ? (MASK_FIELD(PLLMUL, pllmul, PLLMUL_SZ) | MASK_TARGET_WORD):\        ~MASK_FIELD(PLLMUL, 0xf, PLLMUL_SZ))     &\       (plldiv ? (MASK_BIT(PLLDIV) | MASK_TARGET_WORD) :\        ~MASK_BIT(PLLDIV))            &\       (pllcount ? (MASK_FIELD(PLLCOUNT,pllcount, PLLCOUNT_SZ) | MASK_TARGET_WORD):\        ~MASK_FIELD(PLLCOUNT,0x7f, PLLCOUNT_SZ)) &\       (pllonoff ? (MASK_BIT(PLLONOFF) | MASK_TARGET_WORD): \        ~MASK_BIT(PLLONOFF))        &\       (pllndiv ? MASK_BIT(PLLNDIV) | MASK_TARGET_WORD :\        ~MASK_BIT(PLLNDIV)))/******************************************************************//* CLOCK_RESET(ctrl) - resets clock mode register                 *//*    ctrl - mask to set control register                         *//******************************************************************/#define CLOCK_RESET(ctrl)\	CLKMD = ctrl