?? hostctrl.h
字號:
/*-----------------------------------------------------------------------------
$File: //hodad/usblink/3.4/source/hostctrl/otg242/hostctrl.h $
$DateTime: 2003/11/21 14:48:39 $
$Revision: #2 $
Purpose: OTG242 host controller data and macro definitions.
CONFIDENTIAL AND PROPRIETARY INFORMATION OF SOFTCONNEX TECHNOLOGIES, INC.
THIS NOTICE IS NOT TO BE DELETED, MODIFIED, MOVED OR CHANGED IN ANY WAY.
Copyright (c) 1999 - 2003 by SoftConnex Technologies, Inc.
This software is protected by copyright laws and international copyright
treaties, as well as other intellectual property laws and treaties. This
software is a CONFIDENTIAL, unpublished work of authorship, and with portions
constituting TRADE SECRETS of SoftConnex Technologies, Inc., a Delaware USA
corporation. Any unauthorized use, disclosure, and/or reproduction of this
software, or any part of this software; or distribution of this software in any
form or by any means; or storage of this software in any database or retrieval
system, without the express written consent of, and license from, SoftConnex
Technologies, Inc. is strictly prohibited. This software is protected under the
copyright and/or trade secret laws in other countries in addition to USA. All
Rights Reserved. Failure to abide by the use, disclosure and/or reproduction
restrictions may result in civil and /or criminal penalties, and will be
prosecuted to the maximum extent of the law.
-----------------------------------------------------------------------------*/
#ifndef _SOFTCONNEX_OTG242HC_H_
#define _SOFTCONNEX_OTG242HC_H_
#include "ohcihc.h"
#include "ohcied.h"
#include "ohcitd.h"
#include "etd.h"
#if 0
#define OTG242_HARDWARE_FPGA 0
#define OTG242_HARDWARE_CHIP (~OTG242_HARDWARE_FPGA & 0x1)
#endif
#define OTG242_CHIP_REV_A 0x00000000
#define OTG242_CHIP_REV_B 0x00000001
#define OTG242HC_INTR_SCHEDULE_OVERRUN 0x00000001
#define OTG242HC_INTR_WRITE_DONE_HEAD 0x00000002
#define OTG242HC_INTR_START_OF_FRAME 0x00000004
#define OTG242HC_INTR_RESUME_DETECT 0x00000008
#define OTG242HC_INTR_UNRECOVERABLE_ERROR 0x00000010
#define OTG242HC_INTR_FRAME_NO_OVERFLOW 0x00000020
#define OTG242HC_INTR_ROOT_HUB_STATUS_CHANGE 0x00000040
#define OTG242HC_CTRL 0x80
#define OTG242HC_INTR_STATUS 0x88
#define OTG242HC_INTR_ENABLE 0x8C
#define OTG242HC_XBUFFERINTERRUPTSTATUS 0x98
#define OTG242HC_YBUFFERINTERRUPTSTATUS 0x9C
#define OTG242HC_XYINTERRUPTENABLES 0xA0
#define OTG242HC_XBUFFILLEDSTATUS 0xA8
#define OTG242HC_YBUFFILLEDSTATUS 0xAC
#define OTG242HC_ETD_ENABLE 0xC0
#define OTG242HC_IMMEDIATE_INTR 0xCC
#define OTG242HC_ENDPOINTDONESTATUS 0xD0
#define OTG242HC_ETDDONEENABLE 0xD4
#define OTG242HC_FRAME_NUMBER 0xE0
#define OTG242HC_LS_THRESHOLD 0xE4
#define OTG242HC_RH_DESCRIPTOR_A 0xE8
#define OTG242HC_RH_DESCRIPTOR_B 0xEC
#define OTG242HC_RH_STATUS 0xF0
#define OTG242HC_RH_PORT1_STATUS 0xF4
#define OTG242HC_RH_PORT2_STATUS 0xF8
#define OTG242HC_REVISION_REVISION 0x000000FF
#if 0
#define OTG242HC_REVISION_FPGA 0x00000000
#define OTG242HC_REVISION_CHIP 0x00000000
#if OTG242_HARDWARE_FPGA
#define OTG242HC_REVISION OTG242HC_REVISION_FPGA
#elif OTG242_HARDWARE_CHIP
#define OTG242HC_REVISION OTG242HC_REVISION_CHIP
#else
#error("(hostctrl.h): ERROR no hardware define")
#endif
#endif
#define OTG242HC_CTRL_CBSR 0x00000003
#define OTG242HC_CTRL_HCFS 0x0000000C
#define OTG242HC_CTRL_RWE 0x00000010
#define OTG242HC_CTRL_CBSR_1TO1 0x00000000
#define OTG242HC_CTRL_CBSR_2TO1 0x00000001
#define OTG242HC_CTRL_CBSR_3TO1 0x00000002
#define OTG242HC_CTRL_CBSR_4TO1 0x00000003
#define OTG242HC_CMD_STATUS_HCR 0x80000000
#define OTG242HC_CMD_STATUS_SOC 0x00030000
#define OTG242HC_FM_REMAINING_FRT 0x80000000
#define OTG242HC_CTRL_HCFS_RESET 0x00000000
#define OTG242HC_CTRL_HCFS_RESUME 0x00000004
#define OTG242HC_CTRL_HCFS_OPERATIONAL 0x00000008
#define OTG242HC_CTRL_HCFS_SUSPEND 0x0000000C
#define OTG242HC_CTRL_HCFS_FROM_OHCI(val) ((val & OHCI_HC_CTRL_HCFS) >> 4)
#define OTG242HC_CTRL_RWE_FROM_OHCI(val) ((val & OHCI_HC_CTRL_RWE) >> 6)
#define OTG242HC_CTRL_HCFS_TO_OHCI(val) ((val & OTG242HC_CTRL_HCFS) << 4)
#define OTG242HC_CTRL_RWE_TO_OHCI(val) ((val & OTG242HC_CTRL_RWE) << 6)
#define OTG242HC_CMD_STATUS_HCR_TO_OHCI(val) ((val & OTG242HC_CMD_STATUS_HCR) >> 31)
#define OTG242HC_CMD_STATUS_SOC_TO_OHCI(val) ((val & OTG242HC_CMD_STATUS_SOC))
#define OTG242HC_FRAME_REMAINING_FRT_TO_OHCI(val) ((val & OTG242HC_FM_REMAINING_FRT))
#define OTG242HC_RH_PORT_STATUS(n) (OTG242HC_RH_PORT1_STATUS + ((n - 1) << 2))
#define OTG242HC_RH_PORT_STATUS_CCS 0x00000001
#define OTG242HC_RH_PORT_STATUS_PES 0x00000002
#define OTG242HC_RH_PORT_STATUS_PSS 0x00000004
#define OTG242HC_RH_PORT_STATUS_POCI 0x00000008
#define OTG242HC_RH_PORT_STATUS_PRS 0x00000010
#define OTG242HC_RH_PORT_STATUS_PPS 0x00000100
#define OTG242HC_RH_PORT_STATUS_LSDA 0x00000200
#define OTG242HC_RH_PORT_STATUS_CSC 0x00010000
#define OTG242HC_RH_PORT_STATUS_PESC 0x00020000
#define OTG242HC_RH_PORT_STATUS_PSSC 0x00040000
#define OTG242HC_RH_PORT_STATUS_OCIC 0x00080000
#define OTG242HC_RH_PORT_STATUS_PRSC 0x00100000
#define OTG242HC_RH_PORT_STATUS_CHANGE \
( \
OTG242HC_RH_PORT_STATUS_CSC | \
OTG242HC_RH_PORT_STATUS_PESC | \
OTG242HC_RH_PORT_STATUS_PSSC | \
OTG242HC_RH_PORT_STATUS_OCIC | \
OTG242HC_RH_PORT_STATUS_PRSC \
)
#define OTG242HC_RH_PORT_FIRST 1
#define OTG242HC_RH_PORT_MAX 2
#define OTG242HC_RH_OTG_PORT OTG242HC_RH_PORT_FIRST
#define OTG242HC_START_ADDRESS_ETD 0x200
#define OTG242HC_START_ADDRESS_DATA 0x1000
#define OTG242HC_REGISTER_MAX (0x54 + 4 * OTG242HC_RH_PORT_MAX)
#define OTG242HC_HC_BASE OTG242HC_REGISTER_MAX
#define OTG242HC_HCCA_INTR(hc, num) (hc->hcca + num)
#define OTG242HC_HCCA_FRAME_NUMBER(hc) ((U16 *)(hc->hcca + 0x20))
#define OTG242HC_HCCA_DONE_HEAD(hc) (hc->hcca + 0x21)
struct _Otg242;
typedef struct _Otg242Hc
{
U32 ohciRegMap[256 / sizeof(U32)];
U32* ohciReg;
volatile U8* regBase;
U32* hcca;
U32 intrEnable;
U32 frameNo;
U32 previousFrameNo;
U32 etdIntrEnable;
U32 bulkMemorySize;
SctSemaphore regLock;
U32 freeEtdCount;
Otg242EtdBank etdBank[OTG242ETD_MAX];
struct _Otg242* otg;
}
Otg242Hc;
#define OTG242HC_GetOHCIRegisterBase(hc) ((hc)->ohciReg)
#define OTG242HC_ReadReg(hc, reg) HW_ReadOtg242Register(hc->regBase, reg)
#define OTG242HC_WriteReg(hc, reg, val) HW_WriteOtg242Register(hc->regBase, reg, val)
#define OTG242HC_ReadReg16(hc, reg) HW_ReadOtg242Register16(hc->regBase, reg)
#define OTG242HC_WriteReg16(hc, reg, val) HW_WriteOtg242Register16(hc->regBase, reg, val)
#define OTG242HC_GetBulkMemorySize(hc) (hc->bulkMemorySize)
#define OTG242HC_IncFreeEtd(hc) (hc->freeEtdCount++)
#define OTG242HC_DecFreeEtd(hc) (hc->freeEtdCount--)
#define OTG242HC_GetHcCommandStatus(hc) \
(hc->ohciReg[OHCI_HC_CMD_STATUS / sizeof(U32)])
#define OTG242HC_SetHcCommandStatus(hc, status) \
hc->ohciReg[OHCI_HC_CMD_STATUS / sizeof(U32)] = status
#define OTG242HC_AddHcCommandStatus(hc, status) \
hc->ohciReg[OHCI_HC_CMD_STATUS / sizeof(U32)] |= status
#define OTG242HC_GetHcControlHeadEd(hc) \
(hc->ohciReg[OHCI_HC_CTRL_HEAD_ED / sizeof(U32)])
#define OTG242HC_SetHcControlHeadEd(hc, ed) \
hc->ohciReg[OHCI_HC_CTRL_HEAD_ED / sizeof(U32)] = ed
#define OTG242HC_GetHcControlCurrentEd(hc) \
(hc->ohciReg[OHCI_HC_CTRL_CURRENT_ED / sizeof(U32)])
#define OTG242HC_SetHcControlCurrentEd(hc, ed) \
hc->ohciReg[OHCI_HC_CTRL_CURRENT_ED / sizeof(U32)] = ed
#define OTG242HC_GetHcBulkHeadEd(hc) \
(hc->ohciReg[OHCI_HC_BULK_HEAD_ED / sizeof(U32)])
#define OTG242HC_SetHcBulkHeadEd(hc, ed) \
hc->ohciReg[OHCI_HC_BULK_HEAD_ED / sizeof(U32)] = ed
#define OTG242HC_GetHcBulkCurrentEd(hc) \
(hc->ohciReg[OHCI_HC_BULK_CURRENT_ED / sizeof(U32)])
#define OTG242HC_SetHcBulkCurrentEd(hc, ed) \
hc->ohciReg[OHCI_HC_BULK_CURRENT_ED / sizeof(U32)] = ed
#define OTG242HC_GetHcDoneHead(hc) \
(hc->ohciReg[OHCI_HC_DONE_HEAD / sizeof(U32)])
#define OTG242HC_SetHcDoneHead(hc, ed) \
hc->ohciReg[OHCI_HC_DONE_HEAD / sizeof(U32)] = (U32)ed
#define OTG242HC_GetHcIntrStatus(hc) \
(hc->ohciReg[OHCI_HC_INTR_STATUS / sizeof(U32)])
#define OTG242HC_SetHcIntrStatus(hc, intr) \
hc->ohciReg[OHCI_HC_INTR_STATUS / sizeof(U32)] |= intr
#define OTG242HC_GetHcIntrEnable(hc) \
(hc->ohciReg[OHCI_HC_INTR_ENABLE / sizeof(U32)])
#define OTG242HC_AllocateMemory(hc, length) OTG242_AllocateMemory(hc->otg, length)
#define OTG242HC_FreeMemory(hc, addr) OTG242_FreeMemory(hc->otg, addr)
void OTG242HC_ResumeFromPowerSaveMode(Otg242Hc *hc);
U32 OTG242HC_IntrHandler(Otg242Hc *hc);
SctStatus OTG242HC_Create(Otg242Hc *hc, struct _Otg242 *otg);
SctStatus OTG242HC_Initialize(Otg242Hc *hc);
void OTG242HC_Delete(Otg242Hc *hc);
void OTG242HC_Operational(Otg242Hc *hc);
void OTG242HC_RhStatusWrite(Otg242Hc *hc, U32 val);
void OTG242HC_CommandStatusWrite(Otg242Hc *hc, U32 *reg, U32 val);
void OTG242HC_DoIsocList(Otg242Hc *hc);
void OTG242HC_DoPeriodicList(Otg242Hc *hc);
void OTG242HC_DoCtrlList(Otg242Hc *hc);
void OTG242HC_DoBulkList(Otg242Hc *hc);
void OTG242HC_ReadFromChip(Otg242Hc *hc, U32 dest, U32 hc_mem, U32 len, U32 endPage);
void OTG242HC_WriteToChip(Otg242Hc *hc, U32 source, U32 hc_mem, U32 len, U32 endPage);
void OTG242HC_ReadEtdFromChip(Otg242Hc *hc, Otg242Etd *etd, S32 index);
void OTG242HC_WriteEtdToChip(Otg242Hc *hc, Otg242Etd *etd, S32 index);
#endif
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -