/*-----------------------------------------------------------------------------
$File: //hodad/usblink/3.4/source/hostctrl/otg242/top.h $
$DateTime: 2003/11/21 17:09:53 $
$Revision: #5 $
Purpose:   OTG242 chip level data and macro definitions

CONFIDENTIAL AND PROPRIETARY INFORMATION OF SOFTCONNEX TECHNOLOGIES, INC.

THIS NOTICE IS NOT TO BE DELETED, MODIFIED, MOVED OR CHANGED IN ANY WAY.

Copyright (c) 1999 - 2003 by SoftConnex Technologies, Inc. 

This software is protected by copyright laws and international copyright 
treaties, as well as other intellectual property laws and treaties.  This
software is a CONFIDENTIAL, unpublished work of authorship, and with portions 
constituting TRADE SECRETS of SoftConnex Technologies, Inc., a Delaware USA 
corporation.  Any unauthorized use, disclosure, and/or reproduction of this 
software, or any part of this software; or distribution of this software in any 
form or by any means; or storage of this software in any database or retrieval 
system, without the express written consent of, and license from, SoftConnex 
Technologies, Inc. is strictly prohibited.  This software is protected under the
copyright and/or trade secret laws in other countries in addition to USA.  All 
Rights Reserved.  Failure to abide by the use, disclosure and/or reproduction 
restrictions may result in civil and /or criminal penalties, and will be 
prosecuted to the maximum extent of the law.
-----------------------------------------------------------------------------*/

#ifndef _SOFTCONNEX_TOP_H_
#define _SOFTCONNEX_TOP_H_

#include "mem.h"
#include "hostctrl.h"
#include "functrl.h"
#include "hnp.h"



#define DEFAULT_THCD_IST_PRIORITY      101 /* UsbDriverThread */
#define RELATIVE_PRIO_RESET            1     /* ResetPort */
#define RELATIVE_PRIO_STSCHG           1     /* DeviceStatusChange */

#define OTG242_MODE                    0x00
#define OTG242_INTR_STATUS             0x04
#define OTG242_INTR_ENABLE             0x08
#define OTG242_CLOCK_CONTROL           0x0C
#define OTG242_RESET_CONTROL           0x10 /* ADDED NEW 242 */
#define OTG242_FRAMEINTERVAL           0x14 /* ADDED NEW 242 */
#define OTG242_FRAMEREMAINING          0x18 /* ADDED NEW 242 */
#define OTG242_HNPCONTROLSTATUS        0x1C /* ADDED NEW 242 */
#define OTG242_TIMER_I                 0x20
#define OTG242_TIMER_II                0x24
#define OTG242_TIMER_IIIPULSECONTROL   0x28 /* ADDED NEW 242 */
#define OTG242_HNPINTERRUPTSTATUS      0x2C /* ADDED NEW 242 */
#define OTG242_HNPINTERRUPTSTATUSENABLE 0x30 /* ADDED NEW 242 */
#define OTG242_IO_CONFIGURATION        0x34 /* CHANGE FROM  OTG242_IO_CONFIGURATION_I */
#define OTG242_REVISION                0x3C 

/* IO CONFIGURATION */

#define OTG242_IO_DEBUGCTRL            0xF0000000 /* HardwareDebugControl */
#define OTG242_IO_VBUSCTRL             0x07000000 /* MiscPadDriveStrengthControl */
#define OTG242_IO_VBPCTRL              0x00800000 /* VBPPadPullUpControl */
#define OTG242_IO_INTCTRL              0x003F0000 /* InterruptPadControl */
#define OTG242_IO_CPUCTRL              0x00007000 /* CPUPadControl */
#define OTG242_IO_ADDRCTRL             0x00000700 /* AddressPadControl */
#define OTG242_IO_DATACTRL             0x0000007F /* DataPadControl */

/* System Interrupt   */

#define OTG242_INTR_HC                 0x00000001
#define OTG242_INTR_FC                 0x00000002
#define OTG242_INTR_HNP                0x00000004
#define OTG242_INTR_ASHC               0x00000008 /* AsynchronousHostInterrupt */
#define OTG242_INTR_ASFC               0x00000010 /* AsynchronousFunctionInterrupt */
#define OTG242_INTR_ASHNP              0x00000020 /* AsynchronousHnpInterrupt */
#define OTG242_INTR_WKUPDONE           0x00000040 /* WakeUpDoneInterrupt */

/* hnp interrupt */
#define OTG242_INTR_IDCHANGE           0x00000001 /* IDChangeInterrupt */
#define OTG242_INTR_MASSLVCHG          0x00000002 /* MasterSlaveChangeInterrupt */
#define OTG242_INTR_AVBUSVAILD         0x00000004 /* AVBusValidChangeInterrupt */
#define OTG242_INTR_ASESSVAILD         0x00000008 /* ASessionValidChangeInterrupt */
#define OTG242_INTR_VBUSERROR          0x00000010 /* VBusErrorInterrupt */
#define OTG242_INTR_SRPINT             0x00000020 /* SessionRequestInterrupt */
#define OTG242_INTR_SRPSUCFAIL         0x00000040 /* SrpSuccessFailInterrupt */
#define OTG242_INTR_AIDLEBDTO          0x00000080 /* AIdleBDisconnectTimeOutInterrupt */
#define OTG242_INTR_AWAITBTO           0x00000100 /* AWaitBConnectTimeOutInterrupt */


/* Masks for CORE_ClockControl - address: 0x0C */
#define OTG242_STARTBYPASS             0x00001000               /* StartupTimerBypass */
#define OTG242_STARTCTRL               0x00000F00              /* StartupTimerControl */
#define OTG242_MCLKFREQSEL             0x000000C0              /* MClkFrequencySelect */
#define OTG242_MCLKFREQSEL_48MH        0x00000000              /* MClkFrequencySelect */
#define OTG242_MCLKFREQSEL_24MH        0x00000040              /* MClkFrequencySelect */
#define OTG242_WKUPST                  0x00000008              /* WKUPST */
#define OTG242_FUNCCLK                 0x00000004              /* FunctionClockEnable */
#define OTG242_HSTCLK                  0x00000002              /* HostClockEnable */
#define OTG242_MAINCLK                 0x00000001              /* MainClockEnable */

/* CORE_ResetControl (Address: 0x10) */

#define OTG242_RSTCTRL                 0x00000020              /* ResetControlLogic */
#define OTG242_RSTFC                   0x00000010              /* ResetFunctionController */
#define OTG242_RSTFSIE                 0x00000008              /* ResetFunctionSIE */
#define OTG242_RSTRH                   0x00000004              /* ResetRootHub  */
#define OTG242_RSTHSIE                 0x00000002              /* ResetHostSIE */
#define OTG242_RSTHC                   0x00000001              /* ResetHostController */


#define OTG242_TIMER_IIAWaitBResetMask 0x00007C00
#define OTG242_TIMER_IISrpVPulseWidth  0x000003E0

/* System Interrupt status  */
#define OTG242_INTR_STATUS_HC          0x00000001
#define OTG242_INTR_STATUS_FC          0x00000002
#define OTG242_INTR_STATUS_HNP         0x00000004
#define OTG242_INTR_STATUS_ASHC        0x00000008 /* AsynchronousHostInterrupt */
#define OTG242_INTR_STATUS_ASFC        0x00000010 /* AsynchronousFunctionInterrupt */
#define OTG242_INTR_STATUS_ASHNP       0x00000020 /* AsynchronousHnpInterrupt */
#define OTG242_INTR_STATUS_WKUPDONE    0x00000040 /* WakeUpDoneInterrupt */

/* hnp interrupt status */
#define OTG242_INTR_STATUS_IDCHANGE    0x00000001 /* IDChangeInterrupt */
#define OTG242_INTR_STATUS_MASSLVCHG   0x00000002 /* MasterSlaveChangeInterrupt */
#define OTG242_INTR_STATUS_AVBUSVAILD  0x00000004 /* AVBusValidChangeInterrupt */
#define OTG242_INTR_STATUS_ASESSVAILD  0x00000008 /* ASessionValidChangeInterrupt */
#define OTG242_INTR_STATUS_VBUSERROR   0x00000010 /* VBusErrorInterrupt */
#define OTG242_INTR_STATUS_SRPINT      0x00000020 /* SessionRequestInterrupt */
#define OTG242_INTR_STATUS_SRPSUCFAIL  0x00000040 /* SrpSuccessFailInterrupt */
#define OTG242_INTR_STATUS_AIDLEBDTO   0x00000080 /* AIdleBDisconnectTimeOutInterrupt */
#define OTG242_INTR_STATUS_AWAITBTO    0x00000100 /* AWaitBConnectTimeOutInterrupt */


#define OTG242_MODE_TSTMDE                  0x00008000              /* TestMode */
#define OTG242_MODE_HOSTPULLDN              0x00000100              /* HostTransceiverInternalPullDownEnable */
#define OTG242_MODE_INTR_ACTIVE_HIGH        0x00000008
#define OTG242_MODE_BEMDE                   0x00000004              /* BigEndianMode */
#define OTG242_MODE_HF                      0x00000003
#define OTG242_MODE_HF_HARDWARE_HNP         0x00000000
#define OTG242_MODE_HF_FUNCTION_ONLY        0x00000002
#define OTG242_MODE_HF_HOST_ONLY            0x00000001
#define OTG242_MODE_HF_SOFTWARE_HNP         0x00000003



typedef struct _Otg242
   {
   volatile U8* regBase;
   U32 intrNumber;
   U32 osContext;

   U32 intrStatus;
   U32 intrEnable;
   U32 mode;

   Otg242Mem mem;
   Otg242Hc  hc;   
   Otg242Fc  fc;
   Otg242Hnp hnp;

   SctBool isInISR;
   }
Otg242;

SctStatus OTG242_InterruptEnable(U32 driverObject);
U8* OTG242_base( void );
U32 OTG242_Create(volatile U8* baseAddr, U32 intNum, U32 context);
void OTG242_Delete(U32 driverObject);
SctStatus OTG242_Initialize(U32 driverObject);
SctStatus OTG242_Start(U32 driverObject);
OS_INTERRUPT_HANDLER_PROTOTYPE(OTG242_IntrHandler);

#define OTG242_IsInISR(otg)              ((otg)->isInISR)

#define OTG242_GetHcIntrStatus(driver)   OTG242HC_GetHcIntrStatus((&((Otg242*)driver)->hc))
#define OTG242_GetHcIntrEnable(driver)   OTG242HC_GetHcIntrEnable((&((Otg242*)driver)->hc))

#define OTG242_GetOHCIRegisterBase(otg)  OTG242HC_GetOHCIRegisterBase(&((Otg242*)otg)->hc)

#define OTG242_DisableIntr(otg, intr)  \
   { \
      otg->intrEnable &= ~intr; \
      HW_WriteOtg242Register(otg->regBase, OTG242_INTR_ENABLE, otg->intrEnable); \
   }

#define OTG242_EnableIntr(otg, intr)   \
   { \
      otg->intrEnable |= intr; \
      HW_WriteOtg242Register(otg->regBase, OTG242_INTR_ENABLE, otg->intrEnable); \
   }

#define OTG242_AllocateMemory(otg, size) OTG242MEM_Allocate(&otg->mem, size)
#define OTG242_FreeMemory(otg, addr)     OTG242MEM_Free(&otg->mem, addr)

#define OTG242_IsPioReady(otg)           !(HW_ReadOtg242Register(otg->regBase, OTG242_IO_READY) & 1)
#define OTG242_GetFc(otg)                (&otg->fc)
#define OTG242_IsHostMode(otg)           (((otg->mode & OTG242_MODE_HF) == OTG242_MODE_HF_HOST_ONLY) || \
                                         ((otg->mode & OTG242_MODE_HF) == OTG242_MODE_HF_SOFTWARE_HNP))

#define OTG242_GetHc(otg)                (&otg->hc)
#define OTG242_GetIntrNumber(otg)        (otg->intrNumber)

#define TDI242_HCD_NAME_STRING  "TDI242 HCD"
#define TDI242_REVISION_STRING  "1.1.1"
#define TDI242_BUILD_STRING  "1001"

#endif /* _SOFTCONNEX_TOP_H_ */