?? dsp28_mcbsp.h
字號:
Uint16 RCEB12:1; // 12 Receive Channel enable bit
Uint16 RCEB13:1; // 13 Receive Channel enable bit
Uint16 RCEB14:1; // 14 Receive Channel enable bit
Uint16 RCEB15:1; // 15 Receive Channel enable bit
};
union RCERB_REG {
Uint16 all;
struct RCERB_BITS bit;
};
// XCERA control register bit definitions:
struct XCERA_BITS { // bit description
Uint16 XCEA0:1; // 0 Receive Channel enable bit
Uint16 XCEA1:1; // 1 Receive Channel enable bit
Uint16 XCEA2:1; // 2 Receive Channel enable bit
Uint16 XCEA3:1; // 3 Receive Channel enable bit
Uint16 XCEA4:1; // 4 Receive Channel enable bit
Uint16 XCEA5:1; // 5 Receive Channel enable bit
Uint16 XCEA6:1; // 6 Receive Channel enable bit
Uint16 XCEA7:1; // 7 Receive Channel enable bit
Uint16 XCEA8:1; // 8 Receive Channel enable bit
Uint16 XCEA9:1; // 9 Receive Channel enable bit
Uint16 XCEA10:1; // 10 Receive Channel enable bit
Uint16 XCEA11:1; // 11 Receive Channel enable bit
Uint16 XCEA12:1; // 12 Receive Channel enable bit
Uint16 XCEA13:1; // 13 Receive Channel enable bit
Uint16 XCEA14:1; // 14 Receive Channel enable bit
Uint16 XCEA15:1; // 15 Receive Channel enable bit
};
union XCERA_REG {
Uint16 all;
struct XCERA_BITS bit;
};
// XCERB control register bit definitions:
struct XCERB_BITS { // bit description
Uint16 XCEB0:1; // 0 Receive Channel enable bit
Uint16 XCEB1:1; // 1 Receive Channel enable bit
Uint16 XCEB2:1; // 2 Receive Channel enable bit
Uint16 XCEB3:1; // 3 Receive Channel enable bit
Uint16 XCEB4:1; // 4 Receive Channel enable bit
Uint16 XCEB5:1; // 5 Receive Channel enable bit
Uint16 XCEB6:1; // 6 Receive Channel enable bit
Uint16 XCEB7:1; // 7 Receive Channel enable bit
Uint16 XCEB8:1; // 8 Receive Channel enable bit
Uint16 XCEB9:1; // 9 Receive Channel enable bit
Uint16 XCEB10:1; // 10 Receive Channel enable bit
Uint16 XCEB11:1; // 11 Receive Channel enable bit
Uint16 XCEB12:1; // 12 Receive Channel enable bit
Uint16 XCEB13:1; // 13 Receive Channel enable bit
Uint16 XCEB14:1; // 14 Receive Channel enable bit
Uint16 XCEB15:1; // 15 Receive Channel enable bit
};
union XCERB_REG {
Uint16 all;
struct XCERB_BITS bit;
};
// PCR1 control register bit definitions:
struct PCR1_BITS { // bit description
Uint16 CLKRP:1; // 0 Receive Clock polarity
Uint16 CLKXP:1; // 1 Transmit clock polarity
Uint16 FSRP:1; // 2 Receive Frame synchronization polarity
Uint16 FSXP:1; // 3 Transmit Frame synchronization polarity
Uint16 DR_STAT:1; // 4 DR pin status - reserved for this McBSP
Uint16 DX_STAT:1; // 5 DX pin status - reserved for this McBSP
Uint16 CLKS_STAT:1; // 6 CLKS pin status - reserved for 28x -McBSP
Uint16 SCLKME:1; // 7 Enhanced sample clock mode selection bit.
Uint16 CLKRM:1; // 8 Receiver Clock Mode
Uint16 CLKXM:1; // 9 Transmitter Clock Mode.
Uint16 FSRM:1; // 10 Receive Frame Synchronization Mode
Uint16 FSXM:1; // 11 Transmit Frame Synchronization Mode
Uint16 RIOEN:1; // 12 General Purpose I/O Mode - reserved in this 28x-McBSP
Uint16 XIOEN:1; // 13 General Purpose I/O Mode - reserved in this 28x-McBSP
Uint16 IDEL_EN:1; // 14 reserved in this 28x-McBSP
Uint16 rsvd:1 ; // 15 reserved
};
union PCR1_REG {
Uint16 all;
struct PCR1_BITS bit;
};
// RCERC control register bit definitions:
struct RCERC_BITS { // bit description
Uint16 RCEC0:1; // 0 Receive Channel enable bit
Uint16 RCEC1:1; // 1 Receive Channel enable bit
Uint16 RCEC2:1; // 2 Receive Channel enable bit
Uint16 RCEC3:1; // 3 Receive Channel enable bit
Uint16 RCEC4:1; // 4 Receive Channel enable bit
Uint16 RCEC5:1; // 5 Receive Channel enable bit
Uint16 RCEC6:1; // 6 Receive Channel enable bit
Uint16 RCEC7:1; // 7 Receive Channel enable bit
Uint16 RCEC8:1; // 8 Receive Channel enable bit
Uint16 RCEC9:1; // 9 Receive Channel enable bit
Uint16 RCEC10:1; // 10 Receive Channel enable bit
Uint16 RCEC11:1; // 11 Receive Channel enable bit
Uint16 RCEC12:1; // 12 Receive Channel enable bit
Uint16 RCEC13:1; // 13 Receive Channel enable bit
Uint16 RCEC14:1; // 14 Receive Channel enable bit
Uint16 RCEC15:1; // 15 Receive Channel enable bit
};
union RCERC_REG {
Uint16 all;
struct RCERC_BITS bit;
};
// RCERD control register bit definitions:
struct RCERD_BITS { // bit description
Uint16 RCED0:1; // 0 Receive Channel enable bit
Uint16 RCED1:1; // 1 Receive Channel enable bit
Uint16 RCED2:1; // 2 Receive Channel enable bit
Uint16 RCED3:1; // 3 Receive Channel enable bit
Uint16 RCED4:1; // 4 Receive Channel enable bit
Uint16 RCED5:1; // 5 Receive Channel enable bit
Uint16 RCED6:1; // 6 Receive Channel enable bit
Uint16 RCED7:1; // 7 Receive Channel enable bit
Uint16 RCED8:1; // 8 Receive Channel enable bit
Uint16 RCED9:1; // 9 Receive Channel enable bit
Uint16 RCED10:1; // 10 Receive Channel enable bit
Uint16 RCED11:1; // 11 Receive Channel enable bit
Uint16 RCED12:1; // 12 Receive Channel enable bit
Uint16 RCED13:1; // 13 Receive Channel enable bit
Uint16 RCED14:1; // 14 Receive Channel enable bit
Uint16 RCED15:1; // 15 Receive Channel enable bit
};
union RCERD_REG {
Uint16 all;
struct RCERD_BITS bit;
};
// XCERC control register bit definitions:
struct XCERC_BITS { // bit description
Uint16 XCEC0:1; // 0 Receive Channel enable bit
Uint16 XCEC1:1; // 1 Receive Channel enable bit
Uint16 XCEC2:1; // 2 Receive Channel enable bit
Uint16 XCEC3:1; // 3 Receive Channel enable bit
Uint16 XCEC4:1; // 4 Receive Channel enable bit
Uint16 XCEC5:1; // 5 Receive Channel enable bit
Uint16 XCEC6:1; // 6 Receive Channel enable bit
Uint16 XCEC7:1; // 7 Receive Channel enable bit
Uint16 XCEC8:1; // 8 Receive Channel enable bit
Uint16 XCEC9:1; // 9 Receive Channel enable bit
Uint16 XCEC10:1; // 10 Receive Channel enable bit
Uint16 XCEC11:1; // 11 Receive Channel enable bit
Uint16 XCEC12:1; // 12 Receive Channel enable bit
Uint16 XCEC13:1; // 13 Receive Channel enable bit
Uint16 XCEC14:1; // 14 Receive Channel enable bit
Uint16 XCEC15:1; // 15 Receive Channel enable bit
};
union XCERC_REG {
Uint16 all;
struct XCERC_BITS bit;
};
// XCERD control register bit definitions:
struct XCERD_BITS { // bit description
Uint16 XCED0:1; // 0 Receive Channel enable bit
Uint16 XCED1:1; // 1 Receive Channel enable bit
Uint16 XCED2:1; // 2 Receive Channel enable bit
Uint16 XCED3:1; // 3 Receive Channel enable bit
Uint16 XCED4:1; // 4 Receive Channel enable bit
Uint16 XCED5:1; // 5 Receive Channel enable bit
Uint16 XCED6:1; // 6 Receive Channel enable bit
Uint16 XCED7:1; // 7 Receive Channel enable bit
Uint16 XCED8:1; // 8 Receive Channel enable bit
Uint16 XCED9:1; // 9 Receive Channel enable bit
Uint16 XCED10:1; // 10 Receive Channel enable bit
Uint16 XCED11:1; // 11 Receive Channel enable bit
Uint16 XCED12:1; // 12 Receive Channel enable bit
Uint16 XCED13:1; // 13 Receive Channel enable bit
Uint16 XCED14:1; // 14 Receive Channel enable bit
Uint16 XCED15:1; // 15 Receive Channel enable bit
};
union XCERD_REG {
Uint16 all;
struct XCERD_BITS bit;
};
// RCERE control register bit definitions:
struct RCERE_BITS { // bit description
Uint16 RCEE0:1; // 0 Receive Channel enable bit
Uint16 RCEE1:1; // 1 Receive Channel enable bit
Uint16 RCEE2:1; // 2 Receive Channel enable bit
Uint16 RCEE3:1; // 3 Receive Channel enable bit
Uint16 RCEE4:1; // 4 Receive Channel enable bit
Uint16 RCEE5:1; // 5 Receive Channel enable bit
Uint16 RCEE6:1; // 6 Receive Channel enable bit
Uint16 RCEE7:1; // 7 Receive Channel enable bit
Uint16 RCEE8:1; // 8 Receive Channel enable bit
Uint16 RCEE9:1; // 9 Receive Channel enable bit
Uint16 RCEE10:1; // 10 Receive Channel enable bit
Uint16 RCEE11:1; // 11 Receive Channel enable bit
Uint16 RCEE12:1; // 12 Receive Channel enable bit
Uint16 RCEE13:1; // 13 Receive Channel enable bit
Uint16 RCEE14:1; // 14 Receive Channel enable bit
Uint16 RCEE15:1; // 15 Receive Channel enable bit
};
union RCERE_REG {
Uint16 all;
struct RCERE_BITS bit;
};
// RCERF control register bit definitions:
struct RCERF_BITS { // bit description
Uint16 RCEF0:1; // 0 Receive Channel enable bit
Uint16 RCEF1:1; // 1 Receive Channel enable bit
Uint16 RCEF2:1; // 2 Receive Channel enable bit
Uint16 RCEF3:1; // 3 Receive Channel enable bit
Uint16 RCEF4:1; // 4 Receive Channel enable bit
Uint16 RCEF5:1; // 5 Receive Channel enable bit
Uint16 RCEF6:1; // 6 Receive Channel enable bit
Uint16 RCEF7:1; // 7 Receive Channel enable bit
Uint16 RCEF8:1; // 8 Receive Channel enable bit
Uint16 RCEF9:1; // 9 Receive Channel enable bit
Uint16 RCEF10:1; // 10 Receive Channel enable bit
Uint16 RCEF11:1; // 11 Receive Channel enable bit
Uint16 RCEF12:1; // 12 Receive Channel enable bit
Uint16 RCEF13:1; // 13 Receive Channel enable bit
Uint16 RCEF14:1; // 14 Receive Channel enable bit
Uint16 RCEF15:1; // 15 Receive Channel enable bit
};
union RCERF_REG {
Uint16 all;
struct RCERF_BITS bit;
};
// XCERE control register bit definitions:
struct XCERE_BITS { // bit description
Uint16 XCEE0:1; // 0 Receive Channel enable bit
Uint16 XCEE1:1; // 1 Receive Channel enable bit
Uint16 XCEE2:1; // 2 Receive Channel enable bit
Uint16 XCEE3:1; // 3 Receive Channel enable bit
Uint16 XCEE4:1; // 4 Receive Channel enable bit
Uint16 XCEE5:1; // 5 Receive Channel enable bit
Uint16 XCEE6:1; // 6 Receive Channel enable bit
Uint16 XCEE7:1; // 7 Receive Channel enable bit
Uint16 XCEE8:1; // 8 Receive Channel enable bit
Uint16 XCEE9:1; // 9 Receive Channel enable bit
Uint16 XCEE10:1; // 10 Receive Channel enable bit
Uint16 XCEE11:1; // 11 Receive Channel enable bit
Uint16 XCEE12:1; // 12 Receive Channel enable bit
Uint16 XCEE13:1; // 13 Receive Channel enable bit
Uint16 XCEE14:1; // 14 Receive Channel enable bit
Uint16 XCEE15:1; // 15 Receive Channel enable bit
};
union XCERE_REG {
Uint16 all;
struct XCERE_BITS bit;
};
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