---------------------------------------------------------------------------
-- Project: DCT 
-- Revision: 1.0 
-- Date of last Revision: October 2 1999 
-- Designer: Vincenzo Liguori 
-- Created by Xentec Inc. 
-- Copyright (c) 1995-1999 Xentec Inc. & Ocean Logic Pty Ltd 
-- Please review the terms of the license agreement before using this file. 
-- If you are not an authorized user, please destroy this source code file 
-- and notify Xentec, Inc. immediately that you inadvertently received an 
-- unauthorized copy. 1 888 7 XENTEC x22 
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity crossh is port(
  y0, y1, y2, y3, y5, y6, y7 : in std_logic_vector(12 downto 0);
  idct, slx2, sli0, sli1, sli2 : in std_logic;
  slx40, slx41, slx42, slx43 : in std_logic_vector(1 downto 0);
  sel0, sel1, sel2, sel3, sel4, sel5, sel6, sel7 : out std_logic_vector(12 downto 0));
end crossh;

architecture rtl of crossh is
  signal i0, i1, i2 : std_logic_vector(12 downto 0);
  signal xc20, xc21 : std_logic_vector(12 downto 0);
  signal xc40, xc41, xc42, xc43 : std_logic_vector(12 downto 0);
begin

  i0 <= y1 when sli0 = '1' else y0;
  i1 <= y3 when sli1 = '1' else y2;
  i2 <= y5 when sli2 = '1' else y6;
  
  xc20 <= y6 when slx2 = '1' else y2;
  xc21 <= y2 when slx2 = '1' else y6;
  
  process(slx40,slx41,slx42,slx43,i0,i1,i2,y7) begin
    case slx40 is
      when "00" => xc40 <= i0;
      when "01" => xc40 <= i1;
      when "10" => xc40 <= i2;
      when "11" => xc40 <= y7;
      when others => xc40 <= (others => '0');
    end case;
    
    case slx41 is
      when "00" => xc41 <= i0;
      when "01" => xc41 <= i1;
      when "10" => xc41 <= i2;
      when "11" => xc41 <= y7;
      when others => xc41 <= (others => '0');
    end case;
 
     case slx42 is
      when "00" => xc42 <= i0;
      when "01" => xc42 <= i1;
      when "10" => xc42 <= i2;
      when "11" => xc42 <= y7;
      when others => xc42 <= (others => '0');
    end case;
 
     case slx43 is
      when "00" => xc43 <= i0;
      when "01" => xc43 <= i1;
      when "10" => xc43 <= i2;
      when "11" => xc43 <= y7;
      when others => xc43 <= (others => '0');
    end case;    
    
  end process;
  
  sel0 <= xc40 when idct = '1' else y0;
  sel1 <= xc41;
  sel2 <= xc42 when idct = '1' else xc20;
  sel3 <= xc43;
  sel4 <= xc43 when idct = '1' else y0;
  sel5 <= xc42;
  sel6 <= xc41 when idct = '1' else xc21;
  sel7 <= xc40;

end rtl;