1. Directory structure

     * .\src VHDL source files of X_DCT virtual components

     * .\tb  VHDL test bench of X_DCT, test bench configuration
             for RTL simulation, and behavioural model of dual port
             RAM. The test bench includes two instantiations of
             the X_DCT virtual component; the first one performs
             forward discrete cosine transform (FDCT), the second one
             is used for inverse discrete cosine transform (IDCT).

     * .\dat This directory is used by VHDL simulator to write FDCT and IDCT
             output vectors (dct.dat and idct.dat). It also contains two
            'golden' files (dct_golden.dat and idct_golden.dat) for
             simulation correctness checking.

     * .\doc This folder contains documentation related to the X_DCT
             virtual component.

2. Compiling VHDL sources files and starting RTL simulation (for
   ModelSim VHDL simulator users only)

  The project root directory contains the following files:

     * v1_0.mpf  ModelSim project description file

     * vcom.do   ModelSim RTL source and test bench compilation
                 script

     * vsim.do   ModelSim RTL simulation script

     * wave.do   Waveform window setup script

  To start VHDL RTL simulation load the v1_0.mpf project description file
  after ModelSim VHDL simulator invoking. To compile RTL and test bench VHDL
  source file execute compilation script by typing in the ModelSim command
  window:

     do vcom.do

  Then run simulation script:

     do vsim.do

  Waveform window will invoke automatically and the simulation will
  run until an end of the input test vector sequence. The simulation results
  can be checked by observing waveforms and/or by comparing simulation output
  files with the corresponding files containing the expected simulation data.